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gerrit-public.fairphone.software / toolchain / llvm-project / 31ccb51a7f1b6fddaa684095d78c4532598cf51d / . / llvm / test / CodeGen / PowerPC / tls-pic.ll
blob: b7d9298685de5f2b118361c5b5a86f17fc44f69a [file] [log] [blame]
Roman Divacky1bab7052013-12-11 22:25:39 +0000[diff] [blame]1; RUN: llc -march=ppc64 -mcpu=pwr7 -O0 -relocation-model=pic < %s | FileCheck -check-prefix=OPT0 %s
2; RUN: llc -march=ppc64 -mcpu=pwr7 -O1 -relocation-model=pic < %s | FileCheck -check-prefix=OPT1 %s
Hal Finkel0d2a1512015-02-06 23:07:40 +0000[diff] [blame]3; RUN: llc -march=ppc32 -O0 -relocation-model=pic < %s | FileCheck -check-prefix=OPT0-32 %s
4; RUN: llc -march=ppc32 -O1 -relocation-model=pic < %s | FileCheck -check-prefix=OPT1-32 %s
Roman Divacky1bab7052013-12-11 22:25:39 +0000[diff] [blame]5
Tim Northover444eba22013-12-12 11:51:23 +0000[diff] [blame]6target triple = "powerpc64-unknown-linux-gnu"
Roman Divacky1bab7052013-12-11 22:25:39 +0000[diff] [blame]7; Test correct assembly code generation for thread-local storage using
8; the local dynamic model.
9
10@a = hidden thread_local global i32 0, align 4
11
12define signext i32 @main() nounwind {
13entry:
14 %retval = alloca i32, align 4
15 store i32 0, i32* %retval
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]16 %0 = load i32, i32* @a, align 4
Roman Divacky1bab7052013-12-11 22:25:39 +0000[diff] [blame]17 ret i32 %0
18}
19
20; OPT0-LABEL: main:
21; OPT0: addis [[REG:[0-9]+]], 2, a@got@tlsld@ha
Daniel Jasper1d966ef2015-02-10 20:49:05 +0000[diff] [blame]22; OPT0: addi 3, [[REG]], a@got@tlsld@l
Roman Divacky1bab7052013-12-11 22:25:39 +0000[diff] [blame]23; OPT0: bl __tls_get_addr(a@tlsld)
24; OPT0-NEXT: nop
25; OPT0: addis [[REG2:[0-9]+]], 3, a@dtprel@ha
Daniel Jasper1d966ef2015-02-10 20:49:05 +0000[diff] [blame]26; OPT0: addi {{[0-9]+}}, [[REG2]], a@dtprel@l
Hal Finkel7c8ae532014-07-25 17:47:22 +0000[diff] [blame]27; OPT0-32-LABEL: main
Hal Finkel12b607a2015-02-06 23:30:06 +0000[diff] [blame]28; OPT0-32: addi {{[0-9]+}}, {{[0-9]+}}, a@got@tlsld
Hal Finkel7c8ae532014-07-25 17:47:22 +0000[diff] [blame]29; OPT0-32: bl __tls_get_addr(a@tlsld)@PLT
30; OPT0-32: addis [[REG:[0-9]+]], 3, a@dtprel@ha
Daniel Jasper1d966ef2015-02-10 20:49:05 +0000[diff] [blame]31; OPT0-32: addi {{[0-9]+}}, [[REG]], a@dtprel@l
Hal Finkel7c8ae532014-07-25 17:47:22 +0000[diff] [blame]32; OPT1-32-LABEL: main
Bill Schmidt1354f7c2015-02-04 05:51:56 +0000[diff] [blame]33; OPT1-32: addi 3, {{[0-9]+}}, a@got@tlsld
Hal Finkel7c8ae532014-07-25 17:47:22 +0000[diff] [blame]34; OPT1-32: bl __tls_get_addr(a@tlsld)@PLT
35; OPT1-32: addis [[REG:[0-9]+]], 3, a@dtprel@ha
Daniel Jasper1d966ef2015-02-10 20:49:05 +0000[diff] [blame]36; OPT1-32: addi {{[0-9]+}}, [[REG]], a@dtprel@l
Roman Divacky1bab7052013-12-11 22:25:39 +0000[diff] [blame]37
38; Test peephole optimization for thread-local storage using the
39; local dynamic model.
40
41; OPT1-LABEL: main:
42; OPT1: addis [[REG:[0-9]+]], 2, a@got@tlsld@ha
Daniel Jasper1d966ef2015-02-10 20:49:05 +0000[diff] [blame]43; OPT1: addi 3, [[REG]], a@got@tlsld@l
Roman Divacky1bab7052013-12-11 22:25:39 +0000[diff] [blame]44; OPT1: bl __tls_get_addr(a@tlsld)
45; OPT1-NEXT: nop
46; OPT1: addis [[REG2:[0-9]+]], 3, a@dtprel@ha
Daniel Jasper1d966ef2015-02-10 20:49:05 +0000[diff] [blame]47; OPT1: lwa {{[0-9]+}}, a@dtprel@l([[REG2]])
Roman Divacky1bab7052013-12-11 22:25:39 +0000[diff] [blame]48
49; Test correct assembly code generation for thread-local storage using
50; the general dynamic model.
51
52@a2 = thread_local global i32 0, align 4
53
54define signext i32 @main2() nounwind {
55entry:
56 %retval = alloca i32, align 4
57 store i32 0, i32* %retval
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]58 %0 = load i32, i32* @a2, align 4
Roman Divacky1bab7052013-12-11 22:25:39 +0000[diff] [blame]59 ret i32 %0
60}
61
62; OPT1-LABEL: main2
Daniel Jasper1d966ef2015-02-10 20:49:05 +0000[diff] [blame]63; OPT1: addis [[REG:[0-9]+]], 2, a2@got@tlsgd@ha
64; OPT1: addi 3, [[REG]], a2@got@tlsgd@l
Roman Divacky1bab7052013-12-11 22:25:39 +0000[diff] [blame]65; OPT1: bl __tls_get_addr(a2@tlsgd)
66; OPT1-NEXT: nop
Hal Finkel7c8ae532014-07-25 17:47:22 +0000[diff] [blame]67; OPT1-32-LABEL: main2
Hal Finkel0d2a1512015-02-06 23:07:40 +0000[diff] [blame]68; OPT1-32: addi 3, {{[0-9]+}}, a2@got@tlsgd
Hal Finkel7c8ae532014-07-25 17:47:22 +0000[diff] [blame]69; OPT1-32: bl __tls_get_addr(a2@tlsgd)@PLT