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gerrit-public.fairphone.software / toolchain / llvm-project / 31f712556206cdf9ec8e15de11f56b092ac4cdae / . / llvm / lib / Target / Hexagon / HexagonIntrinsicsV4.td
blob: 77b148b9f2bd941f651c6b88f522616f77822474 [file] [log] [blame]
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]1//===- HexagonIntrinsicsV4.td - V4 Instruction intrinsics --*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9// This is populated based on the following specs:
10// Hexagon V4 Architecture Extensions
11// Application-Level Specification
12// 80-V9418-12 Rev. A
13// June 15, 2010
14
15
16//
17// ALU 32 types.
18//
19
20class si_ALU32_sisi_not<string opc, Intrinsic IntID>
21 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
22 !strconcat("$dst = ", !strconcat(opc , "($src1, ~$src2)")),
23 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
24
25class di_ALU32_s8si<string opc, Intrinsic IntID>
26 : ALU32_rr<(outs DoubleRegs:$dst), (ins s8Imm:$src1, IntRegs:$src2),
27 !strconcat("$dst = ", !strconcat(opc , "(#$src1, $src2)")),
28 [(set DoubleRegs:$dst, (IntID imm:$src1, IntRegs:$src2))]>;
29
30class di_ALU32_sis8<string opc, Intrinsic IntID>
31 : ALU32_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
32 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
33 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
34
35class qi_neg_ALU32_sisi<string opc, Intrinsic IntID>
36 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
37 !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")),
38 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
39
40class qi_neg_ALU32_sis10<string opc, Intrinsic IntID>
41 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
42 !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")),
43 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
44
45class qi_neg_ALU32_siu9<string opc, Intrinsic IntID>
46 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2),
47 !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")),
48 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
49
50class si_neg_ALU32_sisi<string opc, Intrinsic IntID>
51 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
52 !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")),
53 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
54
55class si_neg_ALU32_sis8<string opc, Intrinsic IntID>
56 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
57 !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")),
58 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
59
60class si_ALU32_sis8<string opc, Intrinsic IntID>
61 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
62 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
63 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
64
65
66//
67// SInst Classes.
68//
69class qi_neg_SInst_qiqi<string opc, Intrinsic IntID>
70 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
71 !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")),
72 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
73
74class qi_SInst_qi_andqiqi_neg<string opc, Intrinsic IntID>
75 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
76 IntRegs:$src3),
77 !strconcat("$dst = ", !strconcat(opc ,
78 "($src1, and($src2, !$src3)")),
79 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
80 IntRegs:$src3))]>;
81
82class qi_SInst_qi_andqiqi<string opc, Intrinsic IntID>
83 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
84 IntRegs:$src3),
85 !strconcat("$dst = ", !strconcat(opc ,
86 "($src1, and($src2, $src3)")),
87 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
88 IntRegs:$src3))]>;
89
90class qi_SInst_qi_orqiqi_neg<string opc, Intrinsic IntID>
91 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
92 IntRegs:$src3),
93 !strconcat("$dst = ", !strconcat(opc ,
94 "($src1, or($src2, !$src3)")),
95 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
96 IntRegs:$src3))]>;
97
98class qi_SInst_qi_orqiqi<string opc, Intrinsic IntID>
99 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
100 IntRegs:$src3),
101 !strconcat("$dst = ", !strconcat(opc ,
102 "($src1, or($src2, $src3)")),
103 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
104 IntRegs:$src3))]>;
105
106class si_SInst_si_addsis6<string opc, Intrinsic IntID>
107 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, s6Imm:$src3),
108 !strconcat("$dst = ", !strconcat(opc ,
109 "($src1, add($src2, #$src3)")),
110 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
111 imm:$src3))]>;
112
113class si_SInst_si_subs6si<string opc, Intrinsic IntID>
114 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
115 !strconcat("$dst = ", !strconcat(opc ,
116 "($src1, sub(#$src2, $src3)")),
117 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2,
118 IntRegs:$src3))]>;
119
120class di_ALU64_didi_neg<string opc, Intrinsic IntID>
121 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
122 !strconcat("$dst = ", !strconcat(opc , "($src1, ~$src2)")),
123 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
124
125class di_MInst_dididi_xacc<string opc, Intrinsic IntID>
126 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
127 DoubleRegs:$src2),
128 !strconcat("$dst ^= ", !strconcat(opc , "($src1, $src2)")),
129 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
130 DoubleRegs:$src2))],
131 "$dst2 = $dst">;
132
133class si_MInst_sisisi_and<string opc, Intrinsic IntID>
134 : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
135 IntRegs:$src3),
136 !strconcat("$dst &= ", !strconcat(opc , "($src2, $src3)")),
137 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
138 IntRegs:$src3))]>;
139
140class si_MInst_sisisi_andn<string opc, Intrinsic IntID>
141 : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
142 IntRegs:$src3),
143 !strconcat("$dst &= ", !strconcat(opc , "($src2, ~$src3)")),
144 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
145 IntRegs:$src3))]>;
146
147class si_SInst_sisis10_andi<string opc, Intrinsic IntID>
148 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, s10Imm:$src3),
149 !strconcat("$dst = ", !strconcat(opc ,
150 "($src1, and($src2, #$src3))")),
151 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
152 imm:$src3))]>;
153
154class si_MInst_sisisi_xor<string opc, Intrinsic IntID>
155 : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
156 IntRegs:$src3),
157 !strconcat("$dst ^= ", !strconcat(opc , "($src2, $src3)")),
158 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
159 IntRegs:$src3))]>;
160
161class si_MInst_sisisi_xorn<string opc, Intrinsic IntID>
162 : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
163 IntRegs:$src3),
164 !strconcat("$dst ^= ", !strconcat(opc , "($src2, ~$src3)")),
165 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
166 IntRegs:$src3))]>;
167
168class si_SInst_sisis10_or<string opc, Intrinsic IntID>
169 : SInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2, s10Imm:$src3),
170 !strconcat("$dst |= ", !strconcat(opc , "($src2, #$src3)")),
171 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
172 imm:$src3))]>;
173
174class si_MInst_sisisi_or<string opc, Intrinsic IntID>
175 : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
176 IntRegs:$src3),
177 !strconcat("$dst |= ", !strconcat(opc , "($src2, $src3)")),
178 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
179 IntRegs:$src3))]>;
180
181class si_MInst_sisisi_orn<string opc, Intrinsic IntID>
182 : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
183 IntRegs:$src3),
184 !strconcat("$dst |= ", !strconcat(opc , "($src2, ~$src3)")),
185 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
186 IntRegs:$src3))]>;
187
188class si_SInst_siu5_sat<string opc, Intrinsic IntID>
189 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
190 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2):sat")),
191 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
192
193
194/********************************************************************
195* ALU32/ALU *
196*********************************************************************/
197
198// ALU32 / ALU / Logical Operations.
199def Hexagon_A4_orn : si_ALU32_sisi_not <"or", int_hexagon_A4_orn>;
200def Hexagon_A4_andn : si_ALU32_sisi_not <"and", int_hexagon_A4_andn>;
201
202
203/********************************************************************
204* ALU32/PERM *
205*********************************************************************/
206
207// ALU32 / PERM / Combine Words Into Doublewords.
208def Hexagon_A4_combineir : di_ALU32_s8si <"combine", int_hexagon_A4_combineir>;
209def Hexagon_A4_combineri : di_ALU32_sis8 <"combine", int_hexagon_A4_combineri>;
210
211
212/********************************************************************
213* ALU32/PRED *
214*********************************************************************/
215
216// ALU32 / PRED / Conditional Shift Halfword.
217// ALU32 / PRED / Conditional Sign Extend.
218// ALU32 / PRED / Conditional Zero Extend.
219// ALU32 / PRED / Compare.
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]220def Hexagon_C4_cmpltei : qi_neg_ALU32_sis10 <"cmp.gt", int_hexagon_C4_cmpltei>;
Sid Manning31f71252014-09-25 13:09:54 +0000[diff] [blame^]221def Hexagon_C4_cmplte : qi_neg_ALU32_sisi <"cmp.gt", int_hexagon_C4_cmplte>;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]222def Hexagon_C4_cmplteu : qi_neg_ALU32_sisi <"cmp.gtu",int_hexagon_C4_cmplteu>;
Sid Manning31f71252014-09-25 13:09:54 +0000[diff] [blame^]223
224def: T_RI_pat<C4_cmpneqi, int_hexagon_C4_cmpneqi>;
225def: T_RI_pat<C4_cmpltei, int_hexagon_C4_cmpltei>;
226def: T_RI_pat<C4_cmplteui, int_hexagon_C4_cmplteui>;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]227
228// ALU32 / PRED / cmpare To General Register.
229def Hexagon_A4_rcmpneq : si_neg_ALU32_sisi <"cmp.eq", int_hexagon_A4_rcmpneq>;
230def Hexagon_A4_rcmpneqi: si_neg_ALU32_sis8 <"cmp.eq", int_hexagon_A4_rcmpneqi>;
231def Hexagon_A4_rcmpeq : si_ALU32_sisi <"cmp.eq", int_hexagon_A4_rcmpeq>;
232def Hexagon_A4_rcmpeqi : si_ALU32_sis8 <"cmp.eq", int_hexagon_A4_rcmpeqi>;
233
234
235/********************************************************************
236* CR *
237*********************************************************************/
238
239// CR / Corner Detection Acceleration.
240def Hexagon_C4_fastcorner9:
241 qi_SInst_qiqi<"fastcorner9", int_hexagon_C4_fastcorner9>;
242def Hexagon_C4_fastcorner9_not:
243 qi_neg_SInst_qiqi<"fastcorner9",int_hexagon_C4_fastcorner9_not>;
244
245// CR / Logical Operations On Predicates.
246def Hexagon_C4_and_andn:
247 qi_SInst_qi_andqiqi_neg <"and", int_hexagon_C4_and_andn>;
248def Hexagon_C4_and_and:
249 qi_SInst_qi_andqiqi <"and", int_hexagon_C4_and_and>;
250def Hexagon_C4_and_orn:
251 qi_SInst_qi_orqiqi_neg <"and", int_hexagon_C4_and_orn>;
252def Hexagon_C4_and_or:
253 qi_SInst_qi_orqiqi <"and", int_hexagon_C4_and_or>;
254def Hexagon_C4_or_andn:
255 qi_SInst_qi_andqiqi_neg <"or", int_hexagon_C4_or_andn>;
256def Hexagon_C4_or_and:
257 qi_SInst_qi_andqiqi <"or", int_hexagon_C4_or_and>;
258def Hexagon_C4_or_orn:
259 qi_SInst_qi_orqiqi_neg <"or", int_hexagon_C4_or_orn>;
260def Hexagon_C4_or_or:
261 qi_SInst_qi_orqiqi <"or", int_hexagon_C4_or_or>;
262
263
264/********************************************************************
265* XTYPE/ALU *
266*********************************************************************/
267
268// XTYPE / ALU / Add And Accumulate.
269def Hexagon_S4_addaddi:
270 si_SInst_si_addsis6 <"add", int_hexagon_S4_addaddi>;
271def Hexagon_S4_subaddi:
272 si_SInst_si_subs6si <"add", int_hexagon_S4_subaddi>;
273
274// XTYPE / ALU / Logical Doublewords.
275def Hexagon_S4_andnp:
276 di_ALU64_didi_neg <"and", int_hexagon_A4_andnp>;
277def Hexagon_S4_ornp:
278 di_ALU64_didi_neg <"or", int_hexagon_A4_ornp>;
279
280// XTYPE / ALU / Logical-logical Doublewords.
281def Hexagon_M4_xor_xacc:
282 di_MInst_dididi_xacc <"xor", int_hexagon_M4_xor_xacc>;
283
284// XTYPE / ALU / Logical-logical Words.
285def HEXAGON_M4_and_and:
286 si_MInst_sisisi_and <"and", int_hexagon_M4_and_and>;
287def HEXAGON_M4_and_or:
288 si_MInst_sisisi_and <"or", int_hexagon_M4_and_or>;
289def HEXAGON_M4_and_xor:
290 si_MInst_sisisi_and <"xor", int_hexagon_M4_and_xor>;
291def HEXAGON_M4_and_andn:
292 si_MInst_sisisi_andn <"and", int_hexagon_M4_and_andn>;
293def HEXAGON_M4_xor_and:
294 si_MInst_sisisi_xor <"and", int_hexagon_M4_xor_and>;
295def HEXAGON_M4_xor_or:
296 si_MInst_sisisi_xor <"or", int_hexagon_M4_xor_or>;
297def HEXAGON_M4_xor_andn:
298 si_MInst_sisisi_xorn <"and", int_hexagon_M4_xor_andn>;
299def HEXAGON_M4_or_and:
300 si_MInst_sisisi_or <"and", int_hexagon_M4_or_and>;
301def HEXAGON_M4_or_or:
302 si_MInst_sisisi_or <"or", int_hexagon_M4_or_or>;
303def HEXAGON_M4_or_xor:
304 si_MInst_sisisi_or <"xor", int_hexagon_M4_or_xor>;
305def HEXAGON_M4_or_andn:
306 si_MInst_sisisi_orn <"and", int_hexagon_M4_or_andn>;
307def HEXAGON_S4_or_andix:
308 si_SInst_sisis10_andi <"or", int_hexagon_S4_or_andix>;
309def HEXAGON_S4_or_andi:
310 si_SInst_sisis10_or <"and", int_hexagon_S4_or_andi>;
311def HEXAGON_S4_or_ori:
312 si_SInst_sisis10_or <"or", int_hexagon_S4_or_ori>;
313
314// XTYPE / ALU / Modulo wrap.
315def HEXAGON_A4_modwrapu:
316 si_ALU64_sisi <"modwrap", int_hexagon_A4_modwrapu>;
317
318// XTYPE / ALU / Round.
319def HEXAGON_A4_cround_ri:
320 si_SInst_siu5 <"cround", int_hexagon_A4_cround_ri>;
321def HEXAGON_A4_cround_rr:
322 si_SInst_sisi <"cround", int_hexagon_A4_cround_rr>;
323def HEXAGON_A4_round_ri:
324 si_SInst_siu5 <"round", int_hexagon_A4_round_ri>;
325def HEXAGON_A4_round_rr:
326 si_SInst_sisi <"round", int_hexagon_A4_round_rr>;
327def HEXAGON_A4_round_ri_sat:
328 si_SInst_siu5_sat <"round", int_hexagon_A4_round_ri_sat>;
329def HEXAGON_A4_round_rr_sat:
330 si_SInst_sisi_sat <"round", int_hexagon_A4_round_rr_sat>;
331
332// XTYPE / ALU / Vector reduce add unsigned halfwords.
333// XTYPE / ALU / Vector add bytes.
334// XTYPE / ALU / Vector conditional negate.
335// XTYPE / ALU / Vector maximum bytes.
336// XTYPE / ALU / Vector reduce maximum halfwords.
337// XTYPE / ALU / Vector reduce maximum words.
338// XTYPE / ALU / Vector minimum bytes.
339// XTYPE / ALU / Vector reduce minimum halfwords.
340// XTYPE / ALU / Vector reduce minimum words.
341// XTYPE / ALU / Vector subtract bytes.
342
343
344/********************************************************************
345* XTYPE/BIT *
346*********************************************************************/
347
348// XTYPE / BIT / Count leading.
349// XTYPE / BIT / Count trailing.
350// XTYPE / BIT / Extract bitfield.
351// XTYPE / BIT / Masked parity.
352// XTYPE / BIT / Bit reverse.
353// XTYPE / BIT / Split bitfield.
354
355
356/********************************************************************
357* XTYPE/COMPLEX *
358*********************************************************************/
359
360// XTYPE / COMPLEX / Complex add/sub halfwords.
361// XTYPE / COMPLEX / Complex add/sub words.
362// XTYPE / COMPLEX / Complex multiply 32x16.
363// XTYPE / COMPLEX / Vector reduce complex rotate.
364
365
366/********************************************************************
367* XTYPE/MPY *
368*********************************************************************/
369
370// XTYPE / COMPLEX / Complex add/sub halfwords.