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gerrit-public.fairphone.software / toolchain / llvm-project / 322ecd901b52650fcd0ec091a9a01c3483b6f57d / . / llvm / lib / Target / AMDGPU / SIIntrinsics.td
blob: 5da375468713c86722698d4894402694b9991a2c [file] [log] [blame]
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]1//===-- SIIntrinsics.td - SI Intrinsic defs ----------------*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Matt Arsenaulta1fe17c2016-07-19 23:16:53 +0000[diff] [blame]10// Backend internal SI Intrinsic Definitions. User code should not
11// directly use these.
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]12//
13//===----------------------------------------------------------------------===//
14
15
16let TargetPrefix = "SI", isTarget = 1 in {
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]17 def int_SI_packf16 : Intrinsic <[llvm_i32_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
Matt Arsenault7bee6ac2016-12-05 20:23:10 +0000[diff] [blame]18
19 def int_SI_export : Intrinsic <[],
20 [llvm_i32_ty, // en
21 llvm_i32_ty, // vm (FIXME: should be i1)
22 llvm_i32_ty, // done (FIXME: should be i1)
23 llvm_i32_ty, // tgt
24 llvm_i32_ty, // compr (FIXME: should be i1)
25 llvm_float_ty, // src0
26 llvm_float_ty, // src1
27 llvm_float_ty, // src2
28 llvm_float_ty], // src3
29 []
30 >;
31
Tom Stellard9fa17912013-08-14 23:24:45 +0000[diff] [blame]32 def int_SI_load_const : Intrinsic <[llvm_float_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
33 def int_SI_vs_load_input : Intrinsic <[llvm_v4f32_ty], [llvm_anyint_ty, llvm_i16_ty, llvm_i32_ty], [IntrNoMem]> ;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]34
Tom Stellardafcf12f2013-09-12 02:55:14 +0000[diff] [blame]35 // Fully-flexible TBUFFER_STORE_FORMAT_* except for the ADDR64 bit, which is not exposed
36 def int_SI_tbuffer_store : Intrinsic <
37 [],
38 [llvm_anyint_ty, // rsrc(SGPR)
39 llvm_anyint_ty, // vdata(VGPR), overloaded for types i32, v2i32, v4i32
40 llvm_i32_ty, // num_channels(imm), selects opcode suffix: 1=X, 2=XY, 3=XYZ, 4=XYZW
41 llvm_i32_ty, // vaddr(VGPR)
42 llvm_i32_ty, // soffset(SGPR)
43 llvm_i32_ty, // inst_offset(imm)
44 llvm_i32_ty, // dfmt(imm)
45 llvm_i32_ty, // nfmt(imm)
46 llvm_i32_ty, // offen(imm)
47 llvm_i32_ty, // idxen(imm)
48 llvm_i32_ty, // glc(imm)
49 llvm_i32_ty, // slc(imm)
50 llvm_i32_ty], // tfe(imm)
51 []>;
52
Michel Danzer13736222014-01-27 07:20:51 +0000[diff] [blame]53 // Fully-flexible BUFFER_LOAD_DWORD_* except for the ADDR64 bit, which is not exposed
54 def int_SI_buffer_load_dword : Intrinsic <
55 [llvm_anyint_ty], // vdata(VGPR), overloaded for types i32, v2i32, v4i32
56 [llvm_anyint_ty, // rsrc(SGPR)
57 llvm_anyint_ty, // vaddr(VGPR)
58 llvm_i32_ty, // soffset(SGPR)
59 llvm_i32_ty, // inst_offset(imm)
60 llvm_i32_ty, // offen(imm)
61 llvm_i32_ty, // idxen(imm)
62 llvm_i32_ty, // glc(imm)
63 llvm_i32_ty, // slc(imm)
64 llvm_i32_ty], // tfe(imm)
Nicolai Haehnle97788022016-04-21 17:48:02 +0000[diff] [blame]65 [IntrReadMem, IntrArgMemOnly]>;
Michel Danzer13736222014-01-27 07:20:51 +0000[diff] [blame]66
Matt Arsenaultf1341402016-01-23 05:32:18 +0000[diff] [blame]67 def int_SI_sendmsg : Intrinsic <[], [llvm_i32_ty, llvm_i32_ty], []>;
Michel Danzer6064f572014-01-27 07:20:44 +0000[diff] [blame]68
Marek Olsak51b8e7b2014-06-18 22:00:29 +0000[diff] [blame]69 // Fully-flexible SAMPLE instruction.
70 class SampleRaw : Intrinsic <
71 [llvm_v4f32_ty], // vdata(VGPR)
72 [llvm_anyint_ty, // vaddr(VGPR)
Marek Olsakeac50622014-07-11 17:11:52 +0000[diff] [blame]73 llvm_v8i32_ty, // rsrc(SGPR)
74 llvm_v4i32_ty, // sampler(SGPR)
Marek Olsak51b8e7b2014-06-18 22:00:29 +0000[diff] [blame]75 llvm_i32_ty, // dmask(imm)
76 llvm_i32_ty, // unorm(imm)
77 llvm_i32_ty, // r128(imm)
78 llvm_i32_ty, // da(imm)
79 llvm_i32_ty, // glc(imm)
80 llvm_i32_ty, // slc(imm)
81 llvm_i32_ty, // tfe(imm)
82 llvm_i32_ty], // lwe(imm)
83 [IntrNoMem]>;
84
Marek Olsakd8ecaee2014-07-11 17:11:46 +0000[diff] [blame]85 // Image instruction without a sampler.
86 class Image : Intrinsic <
87 [llvm_v4f32_ty], // vdata(VGPR)
88 [llvm_anyint_ty, // vaddr(VGPR)
Marek Olsakeac50622014-07-11 17:11:52 +0000[diff] [blame]89 llvm_v8i32_ty, // rsrc(SGPR)
Marek Olsakd8ecaee2014-07-11 17:11:46 +0000[diff] [blame]90 llvm_i32_ty, // dmask(imm)
91 llvm_i32_ty, // unorm(imm)
92 llvm_i32_ty, // r128(imm)
93 llvm_i32_ty, // da(imm)
94 llvm_i32_ty, // glc(imm)
95 llvm_i32_ty, // slc(imm)
96 llvm_i32_ty, // tfe(imm)
97 llvm_i32_ty], // lwe(imm)
98 [IntrNoMem]>;
99
100 // Basic sample
101 def int_SI_image_sample : SampleRaw;
102 def int_SI_image_sample_cl : SampleRaw;
103 def int_SI_image_sample_d : SampleRaw;
104 def int_SI_image_sample_d_cl : SampleRaw;
105 def int_SI_image_sample_l : SampleRaw;
106 def int_SI_image_sample_b : SampleRaw;
107 def int_SI_image_sample_b_cl : SampleRaw;
108 def int_SI_image_sample_lz : SampleRaw;
109 def int_SI_image_sample_cd : SampleRaw;
110 def int_SI_image_sample_cd_cl : SampleRaw;
111
112 // Sample with comparison
113 def int_SI_image_sample_c : SampleRaw;
114 def int_SI_image_sample_c_cl : SampleRaw;
115 def int_SI_image_sample_c_d : SampleRaw;
116 def int_SI_image_sample_c_d_cl : SampleRaw;
117 def int_SI_image_sample_c_l : SampleRaw;
118 def int_SI_image_sample_c_b : SampleRaw;
119 def int_SI_image_sample_c_b_cl : SampleRaw;
120 def int_SI_image_sample_c_lz : SampleRaw;
121 def int_SI_image_sample_c_cd : SampleRaw;
122 def int_SI_image_sample_c_cd_cl : SampleRaw;
123
124 // Sample with offsets
125 def int_SI_image_sample_o : SampleRaw;
126 def int_SI_image_sample_cl_o : SampleRaw;
127 def int_SI_image_sample_d_o : SampleRaw;
128 def int_SI_image_sample_d_cl_o : SampleRaw;
129 def int_SI_image_sample_l_o : SampleRaw;
130 def int_SI_image_sample_b_o : SampleRaw;
131 def int_SI_image_sample_b_cl_o : SampleRaw;
132 def int_SI_image_sample_lz_o : SampleRaw;
133 def int_SI_image_sample_cd_o : SampleRaw;
134 def int_SI_image_sample_cd_cl_o : SampleRaw;
135
136 // Sample with comparison and offsets
137 def int_SI_image_sample_c_o : SampleRaw;
138 def int_SI_image_sample_c_cl_o : SampleRaw;
139 def int_SI_image_sample_c_d_o : SampleRaw;
140 def int_SI_image_sample_c_d_cl_o : SampleRaw;
141 def int_SI_image_sample_c_l_o : SampleRaw;
142 def int_SI_image_sample_c_b_o : SampleRaw;
143 def int_SI_image_sample_c_b_cl_o : SampleRaw;
144 def int_SI_image_sample_c_lz_o : SampleRaw;
145 def int_SI_image_sample_c_cd_o : SampleRaw;
146 def int_SI_image_sample_c_cd_cl_o : SampleRaw;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]147
Marek Olsak51b8e7b2014-06-18 22:00:29 +0000[diff] [blame]148 // Basic gather4
149 def int_SI_gather4 : SampleRaw;
150 def int_SI_gather4_cl : SampleRaw;
151 def int_SI_gather4_l : SampleRaw;
152 def int_SI_gather4_b : SampleRaw;
153 def int_SI_gather4_b_cl : SampleRaw;
154 def int_SI_gather4_lz : SampleRaw;
155
156 // Gather4 with comparison
157 def int_SI_gather4_c : SampleRaw;
158 def int_SI_gather4_c_cl : SampleRaw;
159 def int_SI_gather4_c_l : SampleRaw;
160 def int_SI_gather4_c_b : SampleRaw;
161 def int_SI_gather4_c_b_cl : SampleRaw;
162 def int_SI_gather4_c_lz : SampleRaw;
163
164 // Gather4 with offsets
165 def int_SI_gather4_o : SampleRaw;
166 def int_SI_gather4_cl_o : SampleRaw;
167 def int_SI_gather4_l_o : SampleRaw;
168 def int_SI_gather4_b_o : SampleRaw;
169 def int_SI_gather4_b_cl_o : SampleRaw;
170 def int_SI_gather4_lz_o : SampleRaw;
171
172 // Gather4 with comparison and offsets
173 def int_SI_gather4_c_o : SampleRaw;
174 def int_SI_gather4_c_cl_o : SampleRaw;
175 def int_SI_gather4_c_l_o : SampleRaw;
176 def int_SI_gather4_c_b_o : SampleRaw;
177 def int_SI_gather4_c_b_cl_o : SampleRaw;
178 def int_SI_gather4_c_lz_o : SampleRaw;
179
180 def int_SI_getlod : SampleRaw;
181
Marek Olsakd8ecaee2014-07-11 17:11:46 +0000[diff] [blame]182 // Image instrinsics.
183 def int_SI_image_load : Image;
184 def int_SI_image_load_mip : Image;
185 def int_SI_getresinfo : Image;
Tom Stellard353b3362013-05-06 23:02:12 +0000[diff] [blame]186
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]187 /* Interpolation Intrinsics */
188
Christian Konig727d06d2013-03-26 14:03:57 +0000[diff] [blame]189 def int_SI_fs_constant : Intrinsic <[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
190 def int_SI_fs_interp : Intrinsic <[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_v2i32_ty], [IntrNoMem]>;
Matt Arsenault7898b902016-01-22 18:42:55 +0000[diff] [blame]191} // End TargetPrefix = "SI", isTarget = 1
Tom Stellardf8794352012-12-19 22:10:31 +0000[diff] [blame]192
Matt Arsenault7898b902016-01-22 18:42:55 +0000[diff] [blame]193let TargetPrefix = "amdgcn", isTarget = 1 in {
Matt Arsenaulta1fe17c2016-07-19 23:16:53 +0000[diff] [blame]194 // Emit 2.5 ulp, no denormal division. Should only be inserted by
195 // pass based on !fpmath metadata.
196 def int_amdgcn_fdiv_fast : Intrinsic<
197 [llvm_float_ty], [llvm_float_ty], [IntrNoMem]
198 >;
199
Tom Stellardf8794352012-12-19 22:10:31 +0000[diff] [blame]200 /* Control flow Intrinsics */
201
Matt Arsenault6408c912016-09-16 22:11:18 +0000[diff] [blame]202 def int_amdgcn_if : Intrinsic<[llvm_i64_ty], [llvm_i1_ty, llvm_empty_ty], [IntrConvergent]>;
203 def int_amdgcn_else : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_empty_ty], [IntrConvergent]>;
204 def int_amdgcn_break : Intrinsic<[llvm_i64_ty], [llvm_i64_ty], [IntrNoMem, IntrConvergent]>;
205 def int_amdgcn_if_break : Intrinsic<[llvm_i64_ty], [llvm_i1_ty, llvm_i64_ty], [IntrNoMem, IntrConvergent]>;
206 def int_amdgcn_else_break : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem, IntrConvergent]>;
207 def int_amdgcn_loop : Intrinsic<[], [llvm_i64_ty, llvm_empty_ty], [IntrConvergent]>;
208 def int_amdgcn_end_cf : Intrinsic<[], [llvm_i64_ty], [IntrConvergent]>;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]209}