blob: 01944601aaf7dbf752b43ddc460ab0db36f9c7db [file] [log] [blame]
Hal Finkel2ebe6d02012-12-25 18:51:18 +00001target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
2target triple = "powerpc64-unknown-linux-gnu"
Ehsan Amiria538b0f2016-08-03 18:17:35 +00003; RUN: llc -verify-machineinstrs -mcpu=a2 -enable-misched -enable-aa-sched-mi < %s | FileCheck %s
Hal Finkel2ebe6d02012-12-25 18:51:18 +00004
5define i8 @test1(i8* noalias %a, i8* noalias %b, i8* noalias %c) nounwind {
6entry:
David Blaikiea79ac142015-02-27 21:17:42 +00007 %q = load i8, i8* %b
Hal Finkel2ebe6d02012-12-25 18:51:18 +00008 call void @llvm.prefetch(i8* %a, i32 0, i32 3, i32 1)
David Blaikiea79ac142015-02-27 21:17:42 +00009 %r = load i8, i8* %c
Hal Finkel2ebe6d02012-12-25 18:51:18 +000010 %s = add i8 %q, %r
11 ret i8 %s
12}
13
14declare void @llvm.prefetch(i8*, i32, i32, i32)
15
16; Test that we've moved the second load to before the dcbt to better
17; hide its latency.
18; CHECK: @test1
19; CHECK: lbz
20; CHECK: lbz
21; CHECK: dcbt
22