| Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 1 | //===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //==-----------------------------------------------------------------------===// |
| 9 | |
| 10 | // Include AMDIL TD files |
| 11 | include "AMDILBase.td" |
| 12 | |
| Tom Stellard | 9979277 | 2013-06-07 20:28:49 +0000 | [diff] [blame] | 13 | //===----------------------------------------------------------------------===// |
| 14 | // Subtarget Features |
| 15 | //===----------------------------------------------------------------------===// |
| 16 | |
| 17 | def FeatureFP64 : SubtargetFeature<"fp64", |
| 18 | "CapsOverride[AMDGPUDeviceInfo::DoubleOps]", |
| 19 | "true", |
| 20 | "Enable 64bit double precision operations">; |
| 21 | def FeatureByteAddress : SubtargetFeature<"byte_addressable_store", |
| 22 | "CapsOverride[AMDGPUDeviceInfo::ByteStores]", |
| 23 | "true", |
| 24 | "Enable byte addressable stores">; |
| 25 | def FeatureBarrierDetect : SubtargetFeature<"barrier_detect", |
| 26 | "CapsOverride[AMDGPUDeviceInfo::BarrierDetect]", |
| 27 | "true", |
| 28 | "Enable duplicate barrier detection(HD5XXX or later).">; |
| 29 | def FeatureImages : SubtargetFeature<"images", |
| 30 | "CapsOverride[AMDGPUDeviceInfo::Images]", |
| 31 | "true", |
| 32 | "Enable image functions">; |
| 33 | def FeatureMultiUAV : SubtargetFeature<"multi_uav", |
| 34 | "CapsOverride[AMDGPUDeviceInfo::MultiUAV]", |
| 35 | "true", |
| 36 | "Generate multiple UAV code(HD5XXX family or later)">; |
| 37 | def FeatureMacroDB : SubtargetFeature<"macrodb", |
| 38 | "CapsOverride[AMDGPUDeviceInfo::MacroDB]", |
| 39 | "true", |
| 40 | "Use internal macrodb, instead of macrodb in driver">; |
| 41 | def FeatureNoAlias : SubtargetFeature<"noalias", |
| 42 | "CapsOverride[AMDGPUDeviceInfo::NoAlias]", |
| 43 | "true", |
| 44 | "assert that all kernel argument pointers are not aliased">; |
| 45 | def FeatureNoInline : SubtargetFeature<"no-inline", |
| 46 | "CapsOverride[AMDGPUDeviceInfo::NoInline]", |
| 47 | "true", |
| 48 | "specify whether to not inline functions">; |
| 49 | |
| 50 | def Feature64BitPtr : SubtargetFeature<"64BitPtr", |
| 51 | "Is64bit", |
| 52 | "false", |
| 53 | "Specify if 64bit addressing should be used.">; |
| 54 | |
| 55 | def Feature32on64BitPtr : SubtargetFeature<"64on32BitPtr", |
| 56 | "Is32on64bit", |
| 57 | "false", |
| 58 | "Specify if 64bit sized pointers with 32bit addressing should be used.">; |
| 59 | def FeatureDebug : SubtargetFeature<"debug", |
| 60 | "CapsOverride[AMDGPUDeviceInfo::Debug]", |
| 61 | "true", |
| 62 | "Debug mode is enabled, so disable hardware accelerated address spaces.">; |
| 63 | def FeatureDumpCode : SubtargetFeature <"DumpCode", |
| 64 | "DumpCode", |
| 65 | "true", |
| 66 | "Dump MachineInstrs in the CodeEmitter">; |
| 67 | |
| 68 | def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst", |
| 69 | "R600ALUInst", |
| 70 | "false", |
| 71 | "Older version of ALU instructions encoding.">; |
| 72 | |
| 73 | def FeatureVertexCache : SubtargetFeature<"HasVertexCache", |
| 74 | "HasVertexCache", |
| 75 | "true", |
| 76 | "Specify use of dedicated vertex cache.">; |
| 77 | |
| Tom Stellard | 3498e4f | 2013-06-07 20:28:55 +0000 | [diff] [blame^] | 78 | class SubtargetFeatureFetchLimit <string Value> : |
| 79 | SubtargetFeature <"fetch"#Value, |
| 80 | "TexVTXClauseSize", |
| 81 | Value, |
| 82 | "Limit the maximum number of fetches in a clause to "#Value>; |
| Tom Stellard | 9979277 | 2013-06-07 20:28:49 +0000 | [diff] [blame] | 83 | |
| Tom Stellard | 3498e4f | 2013-06-07 20:28:55 +0000 | [diff] [blame^] | 84 | def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">; |
| 85 | def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">; |
| 86 | |
| 87 | //===----------------------------------------------------------------------===// |
| Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 88 | |
| 89 | def AMDGPUInstrInfo : InstrInfo { |
| 90 | let guessInstructionProperties = 1; |
| 91 | } |
| 92 | |
| 93 | //===----------------------------------------------------------------------===// |
| 94 | // Declare the target which we are implementing |
| 95 | //===----------------------------------------------------------------------===// |
| 96 | def AMDGPUAsmWriter : AsmWriter { |
| 97 | string AsmWriterClassName = "InstPrinter"; |
| 98 | int Variant = 0; |
| 99 | bit isMCAsmWriter = 1; |
| 100 | } |
| 101 | |
| 102 | def AMDGPU : Target { |
| 103 | // Pull in Instruction Info: |
| 104 | let InstructionSet = AMDGPUInstrInfo; |
| 105 | let AssemblyWriters = [AMDGPUAsmWriter]; |
| 106 | } |
| 107 | |
| 108 | // Include AMDGPU TD files |
| 109 | include "R600Schedule.td" |
| 110 | include "SISchedule.td" |
| 111 | include "Processors.td" |
| 112 | include "AMDGPUInstrInfo.td" |
| 113 | include "AMDGPUIntrinsics.td" |
| 114 | include "AMDGPURegisterInfo.td" |
| 115 | include "AMDGPUInstructions.td" |
| Christian Konig | 2c8f6d5 | 2013-03-07 09:03:52 +0000 | [diff] [blame] | 116 | include "AMDGPUCallingConv.td" |