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gerrit-public.fairphone.software / toolchain / llvm-project / 34da36e74f1f5ab5874f825074f04ecde2be50f4 / . / llvm / test / CodeGen / PowerPC / setcc-logic.ll
blob: 38db2a8bcefc66489ca312cd9de5796543442cca [file] [log] [blame]
Sanjay Patela97d36f2017-03-31 18:51:03 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown | FileCheck %s
3
4define zeroext i1 @all_bits_clear(i32 %P, i32 %Q) {
5; CHECK-LABEL: all_bits_clear:
6; CHECK: # BB#0:
7; CHECK-NEXT: or 3, 3, 4
8; CHECK-NEXT: cntlzw 3, 3
9; CHECK-NEXT: rlwinm 3, 3, 27, 31, 31
10; CHECK-NEXT: blr
11 %a = icmp eq i32 %P, 0
12 %b = icmp eq i32 %Q, 0
13 %c = and i1 %a, %b
14 ret i1 %c
15}
16
17define zeroext i1 @all_sign_bits_clear(i32 %P, i32 %Q) {
18; CHECK-LABEL: all_sign_bits_clear:
19; CHECK: # BB#0:
20; CHECK-NEXT: or 3, 3, 4
21; CHECK-NEXT: nor 3, 3, 3
22; CHECK-NEXT: srwi 3, 3, 31
23; CHECK-NEXT: blr
24 %a = icmp sgt i32 %P, -1
25 %b = icmp sgt i32 %Q, -1
26 %c = and i1 %a, %b
27 ret i1 %c
28}
29
30define zeroext i1 @all_bits_set(i32 %P, i32 %Q) {
31; CHECK-LABEL: all_bits_set:
32; CHECK: # BB#0:
33; CHECK-NEXT: and 3, 3, 4
34; CHECK-NEXT: li 5, 0
35; CHECK-NEXT: li 12, 1
36; CHECK-NEXT: cmpwi 0, 3, -1
37; CHECK-NEXT: isel 3, 12, 5, 2
38; CHECK-NEXT: blr
39 %a = icmp eq i32 %P, -1
40 %b = icmp eq i32 %Q, -1
41 %c = and i1 %a, %b
42 ret i1 %c
43}
44
45define zeroext i1 @all_sign_bits_set(i32 %P, i32 %Q) {
46; CHECK-LABEL: all_sign_bits_set:
47; CHECK: # BB#0:
Sanjay Patel34da36e2017-03-31 20:28:06 +0000[diff] [blame^]48; CHECK-NEXT: and 3, 3, 4
49; CHECK-NEXT: srwi 3, 3, 31
Sanjay Patela97d36f2017-03-31 18:51:03 +0000[diff] [blame]50; CHECK-NEXT: blr
51 %a = icmp slt i32 %P, 0
52 %b = icmp slt i32 %Q, 0
53 %c = and i1 %a, %b
54 ret i1 %c
55}
56
57define zeroext i1 @any_bits_set(i32 %P, i32 %Q) {
58; CHECK-LABEL: any_bits_set:
59; CHECK: # BB#0:
60; CHECK-NEXT: or 3, 3, 4
61; CHECK-NEXT: cntlzw 3, 3
62; CHECK-NEXT: nor 3, 3, 3
63; CHECK-NEXT: rlwinm 3, 3, 27, 31, 31
64; CHECK-NEXT: blr
65 %a = icmp ne i32 %P, 0
66 %b = icmp ne i32 %Q, 0
67 %c = or i1 %a, %b
68 ret i1 %c
69}
70
71define zeroext i1 @any_sign_bits_set(i32 %P, i32 %Q) {
72; CHECK-LABEL: any_sign_bits_set:
73; CHECK: # BB#0:
74; CHECK-NEXT: or 3, 3, 4
75; CHECK-NEXT: srwi 3, 3, 31
76; CHECK-NEXT: blr
77 %a = icmp slt i32 %P, 0
78 %b = icmp slt i32 %Q, 0
79 %c = or i1 %a, %b
80 ret i1 %c
81}
82
83define zeroext i1 @any_bits_clear(i32 %P, i32 %Q) {
84; CHECK-LABEL: any_bits_clear:
85; CHECK: # BB#0:
86; CHECK-NEXT: and 3, 3, 4
87; CHECK-NEXT: li 5, 1
88; CHECK-NEXT: cmpwi 0, 3, -1
89; CHECK-NEXT: isel 3, 0, 5, 2
90; CHECK-NEXT: blr
91 %a = icmp ne i32 %P, -1
92 %b = icmp ne i32 %Q, -1
93 %c = or i1 %a, %b
94 ret i1 %c
95}
96
97define zeroext i1 @any_sign_bits_clear(i32 %P, i32 %Q) {
98; CHECK-LABEL: any_sign_bits_clear:
99; CHECK: # BB#0:
100; CHECK-NEXT: and 3, 3, 4
101; CHECK-NEXT: nor 3, 3, 3
102; CHECK-NEXT: srwi 3, 3, 31
103; CHECK-NEXT: blr
104 %a = icmp sgt i32 %P, -1
105 %b = icmp sgt i32 %Q, -1
106 %c = or i1 %a, %b
107 ret i1 %c
108}
109
110; PR3351 - (P == 0) & (Q == 0) -> (P|Q) == 0
111define i32 @all_bits_clear_branch(i32* %P, i32* %Q) {
112; CHECK-LABEL: all_bits_clear_branch:
113; CHECK: # BB#0: # %entry
114; CHECK-NEXT: or. 3, 3, 4
115; CHECK-NEXT: bne 0, .LBB8_2
116; CHECK-NEXT: # BB#1: # %bb1
117; CHECK-NEXT: li 3, 4
118; CHECK-NEXT: blr
119; CHECK-NEXT: .LBB8_2: # %return
120; CHECK-NEXT: li 3, 192
121; CHECK-NEXT: blr
122entry:
123 %a = icmp eq i32* %P, null
124 %b = icmp eq i32* %Q, null
125 %c = and i1 %a, %b
126 br i1 %c, label %bb1, label %return
127
128bb1:
129 ret i32 4
130
131return:
132 ret i32 192
133}
134
135define i32 @all_sign_bits_clear_branch(i32 %P, i32 %Q) {
136; CHECK-LABEL: all_sign_bits_clear_branch:
137; CHECK: # BB#0: # %entry
138; CHECK-NEXT: or 3, 3, 4
139; CHECK-NEXT: cmpwi 0, 3, 0
140; CHECK-NEXT: blt 0, .LBB9_2
141; CHECK-NEXT: # BB#1: # %bb1
142; CHECK-NEXT: li 3, 4
143; CHECK-NEXT: blr
144; CHECK-NEXT: .LBB9_2: # %return
145; CHECK-NEXT: li 3, 192
146; CHECK-NEXT: blr
147entry:
148 %a = icmp sgt i32 %P, -1
149 %b = icmp sgt i32 %Q, -1
150 %c = and i1 %a, %b
151 br i1 %c, label %bb1, label %return
152
153bb1:
154 ret i32 4
155
156return:
157 ret i32 192
158}
159
160define i32 @all_bits_set_branch(i32 %P, i32 %Q) {
161; CHECK-LABEL: all_bits_set_branch:
162; CHECK: # BB#0: # %entry
163; CHECK-NEXT: and 3, 3, 4
164; CHECK-NEXT: cmpwi 0, 3, -1
165; CHECK-NEXT: bne 0, .LBB10_2
166; CHECK-NEXT: # BB#1: # %bb1
167; CHECK-NEXT: li 3, 4
168; CHECK-NEXT: blr
169; CHECK-NEXT: .LBB10_2: # %return
170; CHECK-NEXT: li 3, 192
171; CHECK-NEXT: blr
172entry:
173 %a = icmp eq i32 %P, -1
174 %b = icmp eq i32 %Q, -1
175 %c = and i1 %a, %b
176 br i1 %c, label %bb1, label %return
177
178bb1:
179 ret i32 4
180
181return:
182 ret i32 192
183}
184
185define i32 @all_sign_bits_set_branch(i32 %P, i32 %Q) {
186; CHECK-LABEL: all_sign_bits_set_branch:
187; CHECK: # BB#0: # %entry
Sanjay Patel34da36e2017-03-31 20:28:06 +0000[diff] [blame^]188; CHECK-NEXT: and 3, 3, 4
189; CHECK-NEXT: cmpwi 0, 3, -1
190; CHECK-NEXT: bgt 0, .LBB11_2
Sanjay Patela97d36f2017-03-31 18:51:03 +0000[diff] [blame]191; CHECK-NEXT: # BB#1: # %bb1
192; CHECK-NEXT: li 3, 4
193; CHECK-NEXT: blr
194; CHECK-NEXT: .LBB11_2: # %return
195; CHECK-NEXT: li 3, 192
196; CHECK-NEXT: blr
197entry:
198 %a = icmp slt i32 %P, 0
199 %b = icmp slt i32 %Q, 0
200 %c = and i1 %a, %b
201 br i1 %c, label %bb1, label %return
202
203bb1:
204 ret i32 4
205
206return:
207 ret i32 192
208}
209
210; PR3351 - (P != 0) | (Q != 0) -> (P|Q) != 0
211define i32 @any_bits_set_branch(i32* %P, i32* %Q) {
212; CHECK-LABEL: any_bits_set_branch:
213; CHECK: # BB#0: # %entry
214; CHECK-NEXT: or. 3, 3, 4
215; CHECK-NEXT: beq 0, .LBB12_2
216; CHECK-NEXT: # BB#1: # %bb1
217; CHECK-NEXT: li 3, 4
218; CHECK-NEXT: blr
219; CHECK-NEXT: .LBB12_2: # %return
220; CHECK-NEXT: li 3, 192
221; CHECK-NEXT: blr
222entry:
223 %a = icmp ne i32* %P, null
224 %b = icmp ne i32* %Q, null
225 %c = or i1 %a, %b
226 br i1 %c, label %bb1, label %return
227
228bb1:
229 ret i32 4
230
231return:
232 ret i32 192
233}
234
235define i32 @any_sign_bits_set_branch(i32 %P, i32 %Q) {
236; CHECK-LABEL: any_sign_bits_set_branch:
237; CHECK: # BB#0: # %entry
238; CHECK-NEXT: or 3, 3, 4
239; CHECK-NEXT: cmpwi 0, 3, -1
240; CHECK-NEXT: bgt 0, .LBB13_2
241; CHECK-NEXT: # BB#1: # %bb1
242; CHECK-NEXT: li 3, 4
243; CHECK-NEXT: blr
244; CHECK-NEXT: .LBB13_2: # %return
245; CHECK-NEXT: li 3, 192
246; CHECK-NEXT: blr
247entry:
248 %a = icmp slt i32 %P, 0
249 %b = icmp slt i32 %Q, 0
250 %c = or i1 %a, %b
251 br i1 %c, label %bb1, label %return
252
253bb1:
254 ret i32 4
255
256return:
257 ret i32 192
258}
259
260define i32 @any_bits_clear_branch(i32 %P, i32 %Q) {
261; CHECK-LABEL: any_bits_clear_branch:
262; CHECK: # BB#0: # %entry
263; CHECK-NEXT: and 3, 3, 4
264; CHECK-NEXT: cmpwi 0, 3, -1
265; CHECK-NEXT: beq 0, .LBB14_2
266; CHECK-NEXT: # BB#1: # %bb1
267; CHECK-NEXT: li 3, 4
268; CHECK-NEXT: blr
269; CHECK-NEXT: .LBB14_2: # %return
270; CHECK-NEXT: li 3, 192
271; CHECK-NEXT: blr
272entry:
273 %a = icmp ne i32 %P, -1
274 %b = icmp ne i32 %Q, -1
275 %c = or i1 %a, %b
276 br i1 %c, label %bb1, label %return
277
278bb1:
279 ret i32 4
280
281return:
282 ret i32 192
283}
284
285define i32 @any_sign_bits_clear_branch(i32 %P, i32 %Q) {
286; CHECK-LABEL: any_sign_bits_clear_branch:
287; CHECK: # BB#0: # %entry
288; CHECK-NEXT: and 3, 3, 4
289; CHECK-NEXT: cmpwi 0, 3, 0
290; CHECK-NEXT: blt 0, .LBB15_2
291; CHECK-NEXT: # BB#1: # %bb1
292; CHECK-NEXT: li 3, 4
293; CHECK-NEXT: blr
294; CHECK-NEXT: .LBB15_2: # %return
295; CHECK-NEXT: li 3, 192
296; CHECK-NEXT: blr
297entry:
298 %a = icmp sgt i32 %P, -1
299 %b = icmp sgt i32 %Q, -1
300 %c = or i1 %a, %b
301 br i1 %c, label %bb1, label %return
302
303bb1:
304 ret i32 4
305
306return:
307 ret i32 192
308}
309