| Vasileios Kalintiris | 3751d41 | 2016-04-13 15:07:45 +0000 | [diff] [blame^] | 1 | ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ |
| 2 | ; RUN: -check-prefix=ALL -check-prefix=PRE-R6 |
| 3 | ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ |
| 4 | ; RUN: -check-prefix=ALL -check-prefix=PRE-R6 |
| 5 | ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ |
| 6 | ; RUN: -check-prefix=ALL -check-prefix=PRE-R6 |
| 7 | ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ |
| 8 | ; RUN: -check-prefix=ALL -check-prefix=PRE-R6 |
| 9 | ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ |
| 10 | ; RUN: -check-prefix=ALL -check-prefix=PRE-R6 |
| 11 | ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ |
| 12 | ; RUN: -check-prefix=ALL -check-prefix=PRE-R6 |
| 13 | ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ |
| 14 | ; RUN: -check-prefix=ALL -check-prefix=R6 |
| 15 | |
| 16 | ; Check that we don't emit redundant SLLs for sequences of |
| 17 | ; (AssertZext:i32 (trunc:i32 (AssertZext:i64 X, i32)), i8) |
| 18 | define zeroext i8 @udiv_i8(i8 zeroext %a, i8 zeroext %b) { |
| 19 | entry: |
| 20 | ; ALL-LABEL: udiv_i8: |
| 21 | |
| 22 | ; PRE-R6-NOT: sll {{.*}} |
| 23 | ; PRE-R6: divu $zero, $4, $5 |
| 24 | ; PRE-R6: teq $5, $zero, 7 |
| 25 | ; PRE-R6: mflo $2 |
| 26 | |
| 27 | ; R6-NOT: sll {{.*}} |
| 28 | ; R6: divu $2, $4, $5 |
| 29 | ; R6: teq $5, $zero, 7 |
| 30 | |
| 31 | %r = udiv i8 %a, %b |
| 32 | ret i8 %r |
| 33 | } |
| 34 | |
| 35 | ; Check that we do sign-extend when we have a (trunc:i32 (AssertZext:i64 X, i32)) |
| 36 | define i64 @foo1(i64 zeroext %var) { |
| 37 | entry: |
| 38 | ; ALL-LABEL: foo1: |
| 39 | |
| 40 | %shr = lshr i64 %var, 32 |
| 41 | %cmp = icmp eq i64 %shr, 0 |
| 42 | br i1 %cmp, label %if.end6, label %if.then |
| 43 | |
| 44 | ; ALL: dsrl $[[T0:[0-9]+]], $4, 32 |
| 45 | ; ALL: sll $[[T1:[0-9]+]], $[[T0]], 0 |
| 46 | if.then: ; preds = %entry |
| 47 | %conv = trunc i64 %shr to i32 |
| 48 | %cmp2 = icmp slt i32 %conv, 0 |
| 49 | br i1 %cmp2, label %if.then4, label %if.else |
| 50 | |
| 51 | if.then4: ; preds = %if.then |
| 52 | %add = add i64 %var, 16 |
| 53 | br label %if.end6 |
| 54 | |
| 55 | if.else: ; preds = %if.then |
| 56 | %add5 = add i64 %var, 32 |
| 57 | br label %if.end6 |
| 58 | |
| 59 | if.end6: ; preds = %entry, %if.then4, %if.else |
| 60 | %var.addr.0 = phi i64 [ %add, %if.then4 ], [ %add5, %if.else ], [ %var, %entry ] |
| 61 | ret i64 %var.addr.0 |
| 62 | } |