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gerrit-public.fairphone.software / toolchain / llvm-project / 9bb601856e8403eaeb4b7920ee1a2c24151fe8ae / . / llvm / lib / Target / Hexagon / HexagonIntrinsicsV4.td
blob: 51ddb1be06f12e2bbb60a9ec9e1cf1dfb618abe9 [file] [log] [blame]
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]1//===- HexagonIntrinsicsV4.td - V4 Instruction intrinsics --*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9// This is populated based on the following specs:
10// Hexagon V4 Architecture Extensions
11// Application-Level Specification
12// 80-V9418-12 Rev. A
13// June 15, 2010
14
Colin LeMahieufe03c9a2015-01-28 17:37:59 +0000[diff] [blame]15// Shift an immediate left by register amount
16def : T_IR_pat<S4_lsli, int_hexagon_S4_lsli>;
17
18// Shift and add/sub/and/or
19def : T_IRI_pat <S4_andi_asl_ri, int_hexagon_S4_andi_asl_ri>;
20def : T_IRI_pat <S4_ori_asl_ri, int_hexagon_S4_ori_asl_ri>;
21def : T_IRI_pat <S4_addi_asl_ri, int_hexagon_S4_addi_asl_ri>;
22def : T_IRI_pat <S4_subi_asl_ri, int_hexagon_S4_subi_asl_ri>;
23def : T_IRI_pat <S4_andi_lsr_ri, int_hexagon_S4_andi_lsr_ri>;
24def : T_IRI_pat <S4_ori_lsr_ri, int_hexagon_S4_ori_lsr_ri>;
25def : T_IRI_pat <S4_addi_lsr_ri, int_hexagon_S4_addi_lsr_ri>;
26def : T_IRI_pat <S4_subi_lsr_ri, int_hexagon_S4_subi_lsr_ri>;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]27
28//
29// ALU 32 types.
30//
31
32class si_ALU32_sisi_not<string opc, Intrinsic IntID>
33 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
34 !strconcat("$dst = ", !strconcat(opc , "($src1, ~$src2)")),
35 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
36
37class di_ALU32_s8si<string opc, Intrinsic IntID>
38 : ALU32_rr<(outs DoubleRegs:$dst), (ins s8Imm:$src1, IntRegs:$src2),
39 !strconcat("$dst = ", !strconcat(opc , "(#$src1, $src2)")),
40 [(set DoubleRegs:$dst, (IntID imm:$src1, IntRegs:$src2))]>;
41
42class di_ALU32_sis8<string opc, Intrinsic IntID>
43 : ALU32_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
44 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
45 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
46
47class qi_neg_ALU32_sisi<string opc, Intrinsic IntID>
48 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
49 !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")),
50 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
51
52class qi_neg_ALU32_sis10<string opc, Intrinsic IntID>
53 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
54 !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")),
55 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
56
57class qi_neg_ALU32_siu9<string opc, Intrinsic IntID>
58 : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2),
59 !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")),
60 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
61
62class si_neg_ALU32_sisi<string opc, Intrinsic IntID>
63 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
64 !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")),
65 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
66
67class si_neg_ALU32_sis8<string opc, Intrinsic IntID>
68 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
69 !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")),
70 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
71
72class si_ALU32_sis8<string opc, Intrinsic IntID>
73 : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
74 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
75 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
76
77
78//
79// SInst Classes.
80//
81class qi_neg_SInst_qiqi<string opc, Intrinsic IntID>
82 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
83 !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")),
84 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
85
86class qi_SInst_qi_andqiqi_neg<string opc, Intrinsic IntID>
87 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
88 IntRegs:$src3),
89 !strconcat("$dst = ", !strconcat(opc ,
90 "($src1, and($src2, !$src3)")),
91 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
92 IntRegs:$src3))]>;
93
94class qi_SInst_qi_andqiqi<string opc, Intrinsic IntID>
95 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
96 IntRegs:$src3),
97 !strconcat("$dst = ", !strconcat(opc ,
98 "($src1, and($src2, $src3)")),
99 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
100 IntRegs:$src3))]>;
101
102class qi_SInst_qi_orqiqi_neg<string opc, Intrinsic IntID>
103 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
104 IntRegs:$src3),
105 !strconcat("$dst = ", !strconcat(opc ,
106 "($src1, or($src2, !$src3)")),
107 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
108 IntRegs:$src3))]>;
109
110class qi_SInst_qi_orqiqi<string opc, Intrinsic IntID>
111 : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
112 IntRegs:$src3),
113 !strconcat("$dst = ", !strconcat(opc ,
114 "($src1, or($src2, $src3)")),
115 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
116 IntRegs:$src3))]>;
117
118class si_SInst_si_addsis6<string opc, Intrinsic IntID>
119 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, s6Imm:$src3),
120 !strconcat("$dst = ", !strconcat(opc ,
121 "($src1, add($src2, #$src3)")),
122 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
123 imm:$src3))]>;
124
125class si_SInst_si_subs6si<string opc, Intrinsic IntID>
126 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
127 !strconcat("$dst = ", !strconcat(opc ,
128 "($src1, sub(#$src2, $src3)")),
129 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2,
130 IntRegs:$src3))]>;
131
132class di_ALU64_didi_neg<string opc, Intrinsic IntID>
133 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
134 !strconcat("$dst = ", !strconcat(opc , "($src1, ~$src2)")),
135 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
136
137class di_MInst_dididi_xacc<string opc, Intrinsic IntID>
138 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
139 DoubleRegs:$src2),
140 !strconcat("$dst ^= ", !strconcat(opc , "($src1, $src2)")),
141 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
142 DoubleRegs:$src2))],
143 "$dst2 = $dst">;
144
145class si_MInst_sisisi_and<string opc, Intrinsic IntID>
146 : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
147 IntRegs:$src3),
148 !strconcat("$dst &= ", !strconcat(opc , "($src2, $src3)")),
149 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
150 IntRegs:$src3))]>;
151
152class si_MInst_sisisi_andn<string opc, Intrinsic IntID>
153 : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
154 IntRegs:$src3),
155 !strconcat("$dst &= ", !strconcat(opc , "($src2, ~$src3)")),
156 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
157 IntRegs:$src3))]>;
158
159class si_SInst_sisis10_andi<string opc, Intrinsic IntID>
160 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, s10Imm:$src3),
161 !strconcat("$dst = ", !strconcat(opc ,
162 "($src1, and($src2, #$src3))")),
163 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
164 imm:$src3))]>;
165
166class si_MInst_sisisi_xor<string opc, Intrinsic IntID>
167 : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
168 IntRegs:$src3),
169 !strconcat("$dst ^= ", !strconcat(opc , "($src2, $src3)")),
170 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
171 IntRegs:$src3))]>;
172
173class si_MInst_sisisi_xorn<string opc, Intrinsic IntID>
174 : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
175 IntRegs:$src3),
176 !strconcat("$dst ^= ", !strconcat(opc , "($src2, ~$src3)")),
177 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
178 IntRegs:$src3))]>;
179
180class si_SInst_sisis10_or<string opc, Intrinsic IntID>
181 : SInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2, s10Imm:$src3),
182 !strconcat("$dst |= ", !strconcat(opc , "($src2, #$src3)")),
183 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
184 imm:$src3))]>;
185
186class si_MInst_sisisi_or<string opc, Intrinsic IntID>
187 : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
188 IntRegs:$src3),
189 !strconcat("$dst |= ", !strconcat(opc , "($src2, $src3)")),
190 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
191 IntRegs:$src3))]>;
192
193class si_MInst_sisisi_orn<string opc, Intrinsic IntID>
194 : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
195 IntRegs:$src3),
196 !strconcat("$dst |= ", !strconcat(opc , "($src2, ~$src3)")),
197 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
198 IntRegs:$src3))]>;
199
200class si_SInst_siu5_sat<string opc, Intrinsic IntID>
201 : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
202 !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2):sat")),
203 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
204
205
206/********************************************************************
207* ALU32/ALU *
208*********************************************************************/
209
210// ALU32 / ALU / Logical Operations.
211def Hexagon_A4_orn : si_ALU32_sisi_not <"or", int_hexagon_A4_orn>;
212def Hexagon_A4_andn : si_ALU32_sisi_not <"and", int_hexagon_A4_andn>;
213
214
215/********************************************************************
216* ALU32/PERM *
217*********************************************************************/
218
219// ALU32 / PERM / Combine Words Into Doublewords.
220def Hexagon_A4_combineir : di_ALU32_s8si <"combine", int_hexagon_A4_combineir>;
221def Hexagon_A4_combineri : di_ALU32_sis8 <"combine", int_hexagon_A4_combineri>;
222
223
224/********************************************************************
225* ALU32/PRED *
226*********************************************************************/
227
228// ALU32 / PRED / Conditional Shift Halfword.
229// ALU32 / PRED / Conditional Sign Extend.
230// ALU32 / PRED / Conditional Zero Extend.
231// ALU32 / PRED / Compare.
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]232def Hexagon_C4_cmpltei : qi_neg_ALU32_sis10 <"cmp.gt", int_hexagon_C4_cmpltei>;
Sid Manning31f71252014-09-25 13:09:54 +0000[diff] [blame]233def Hexagon_C4_cmplte : qi_neg_ALU32_sisi <"cmp.gt", int_hexagon_C4_cmplte>;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]234def Hexagon_C4_cmplteu : qi_neg_ALU32_sisi <"cmp.gtu",int_hexagon_C4_cmplteu>;
Sid Manning31f71252014-09-25 13:09:54 +0000[diff] [blame]235
236def: T_RI_pat<C4_cmpneqi, int_hexagon_C4_cmpneqi>;
237def: T_RI_pat<C4_cmpltei, int_hexagon_C4_cmpltei>;
238def: T_RI_pat<C4_cmplteui, int_hexagon_C4_cmplteui>;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]239
240// ALU32 / PRED / cmpare To General Register.
241def Hexagon_A4_rcmpneq : si_neg_ALU32_sisi <"cmp.eq", int_hexagon_A4_rcmpneq>;
242def Hexagon_A4_rcmpneqi: si_neg_ALU32_sis8 <"cmp.eq", int_hexagon_A4_rcmpneqi>;
243def Hexagon_A4_rcmpeq : si_ALU32_sisi <"cmp.eq", int_hexagon_A4_rcmpeq>;
244def Hexagon_A4_rcmpeqi : si_ALU32_sis8 <"cmp.eq", int_hexagon_A4_rcmpeqi>;
245
246
247/********************************************************************
248* CR *
249*********************************************************************/
250
251// CR / Corner Detection Acceleration.
252def Hexagon_C4_fastcorner9:
253 qi_SInst_qiqi<"fastcorner9", int_hexagon_C4_fastcorner9>;
254def Hexagon_C4_fastcorner9_not:
255 qi_neg_SInst_qiqi<"fastcorner9",int_hexagon_C4_fastcorner9_not>;
256
257// CR / Logical Operations On Predicates.
258def Hexagon_C4_and_andn:
259 qi_SInst_qi_andqiqi_neg <"and", int_hexagon_C4_and_andn>;
260def Hexagon_C4_and_and:
261 qi_SInst_qi_andqiqi <"and", int_hexagon_C4_and_and>;
262def Hexagon_C4_and_orn:
263 qi_SInst_qi_orqiqi_neg <"and", int_hexagon_C4_and_orn>;
264def Hexagon_C4_and_or:
265 qi_SInst_qi_orqiqi <"and", int_hexagon_C4_and_or>;
266def Hexagon_C4_or_andn:
267 qi_SInst_qi_andqiqi_neg <"or", int_hexagon_C4_or_andn>;
268def Hexagon_C4_or_and:
269 qi_SInst_qi_andqiqi <"or", int_hexagon_C4_or_and>;
270def Hexagon_C4_or_orn:
271 qi_SInst_qi_orqiqi_neg <"or", int_hexagon_C4_or_orn>;
272def Hexagon_C4_or_or:
273 qi_SInst_qi_orqiqi <"or", int_hexagon_C4_or_or>;
274
275
276/********************************************************************
277* XTYPE/ALU *
278*********************************************************************/
279
280// XTYPE / ALU / Add And Accumulate.
281def Hexagon_S4_addaddi:
282 si_SInst_si_addsis6 <"add", int_hexagon_S4_addaddi>;
283def Hexagon_S4_subaddi:
284 si_SInst_si_subs6si <"add", int_hexagon_S4_subaddi>;
285
286// XTYPE / ALU / Logical Doublewords.
287def Hexagon_S4_andnp:
288 di_ALU64_didi_neg <"and", int_hexagon_A4_andnp>;
289def Hexagon_S4_ornp:
290 di_ALU64_didi_neg <"or", int_hexagon_A4_ornp>;
291
292// XTYPE / ALU / Logical-logical Doublewords.
293def Hexagon_M4_xor_xacc:
294 di_MInst_dididi_xacc <"xor", int_hexagon_M4_xor_xacc>;
295
296// XTYPE / ALU / Logical-logical Words.
297def HEXAGON_M4_and_and:
298 si_MInst_sisisi_and <"and", int_hexagon_M4_and_and>;
299def HEXAGON_M4_and_or:
300 si_MInst_sisisi_and <"or", int_hexagon_M4_and_or>;
301def HEXAGON_M4_and_xor:
302 si_MInst_sisisi_and <"xor", int_hexagon_M4_and_xor>;
303def HEXAGON_M4_and_andn:
304 si_MInst_sisisi_andn <"and", int_hexagon_M4_and_andn>;
305def HEXAGON_M4_xor_and:
306 si_MInst_sisisi_xor <"and", int_hexagon_M4_xor_and>;
307def HEXAGON_M4_xor_or:
308 si_MInst_sisisi_xor <"or", int_hexagon_M4_xor_or>;
309def HEXAGON_M4_xor_andn:
310 si_MInst_sisisi_xorn <"and", int_hexagon_M4_xor_andn>;
311def HEXAGON_M4_or_and:
312 si_MInst_sisisi_or <"and", int_hexagon_M4_or_and>;
313def HEXAGON_M4_or_or:
314 si_MInst_sisisi_or <"or", int_hexagon_M4_or_or>;
315def HEXAGON_M4_or_xor:
316 si_MInst_sisisi_or <"xor", int_hexagon_M4_or_xor>;
317def HEXAGON_M4_or_andn:
318 si_MInst_sisisi_orn <"and", int_hexagon_M4_or_andn>;
319def HEXAGON_S4_or_andix:
320 si_SInst_sisis10_andi <"or", int_hexagon_S4_or_andix>;
321def HEXAGON_S4_or_andi:
322 si_SInst_sisis10_or <"and", int_hexagon_S4_or_andi>;
323def HEXAGON_S4_or_ori:
324 si_SInst_sisis10_or <"or", int_hexagon_S4_or_ori>;
325
326// XTYPE / ALU / Modulo wrap.
327def HEXAGON_A4_modwrapu:
328 si_ALU64_sisi <"modwrap", int_hexagon_A4_modwrapu>;
329
330// XTYPE / ALU / Round.
331def HEXAGON_A4_cround_ri:
332 si_SInst_siu5 <"cround", int_hexagon_A4_cround_ri>;
333def HEXAGON_A4_cround_rr:
334 si_SInst_sisi <"cround", int_hexagon_A4_cround_rr>;
335def HEXAGON_A4_round_ri:
336 si_SInst_siu5 <"round", int_hexagon_A4_round_ri>;
337def HEXAGON_A4_round_rr:
338 si_SInst_sisi <"round", int_hexagon_A4_round_rr>;
339def HEXAGON_A4_round_ri_sat:
340 si_SInst_siu5_sat <"round", int_hexagon_A4_round_ri_sat>;
341def HEXAGON_A4_round_rr_sat:
342 si_SInst_sisi_sat <"round", int_hexagon_A4_round_rr_sat>;
343
344// XTYPE / ALU / Vector reduce add unsigned halfwords.
345// XTYPE / ALU / Vector add bytes.
346// XTYPE / ALU / Vector conditional negate.
347// XTYPE / ALU / Vector maximum bytes.
348// XTYPE / ALU / Vector reduce maximum halfwords.
349// XTYPE / ALU / Vector reduce maximum words.
350// XTYPE / ALU / Vector minimum bytes.
351// XTYPE / ALU / Vector reduce minimum halfwords.
352// XTYPE / ALU / Vector reduce minimum words.
353// XTYPE / ALU / Vector subtract bytes.
354
355
356/********************************************************************
357* XTYPE/BIT *
358*********************************************************************/
359
360// XTYPE / BIT / Count leading.
361// XTYPE / BIT / Count trailing.
362// XTYPE / BIT / Extract bitfield.
363// XTYPE / BIT / Masked parity.
364// XTYPE / BIT / Bit reverse.
365// XTYPE / BIT / Split bitfield.
366
367
368/********************************************************************
369* XTYPE/COMPLEX *
370*********************************************************************/
371
372// XTYPE / COMPLEX / Complex add/sub halfwords.
373// XTYPE / COMPLEX / Complex add/sub words.
374// XTYPE / COMPLEX / Complex multiply 32x16.
375// XTYPE / COMPLEX / Vector reduce complex rotate.
376
377
378/********************************************************************
379* XTYPE/MPY *
380*********************************************************************/
381
382// XTYPE / COMPLEX / Complex add/sub halfwords.