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Zoran Jovanovicada38ef2014-03-27 12:38:40 +00001//===-- MipsAsmBackend.h - Mips Asm Backend ------------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the MipsAsmBackend class.
11//
12//===----------------------------------------------------------------------===//
13//
14
Benjamin Kramera7c40ef2014-08-13 16:26:38 +000015#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSASMBACKEND_H
16#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSASMBACKEND_H
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000017
18#include "MCTargetDesc/MipsFixupKinds.h"
Daniel Sanders50f17232015-09-15 16:17:27 +000019#include "llvm/ADT/Triple.h"
Chandler Carruthd9903882015-01-14 11:23:27 +000020#include "llvm/MC/MCAsmBackend.h"
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000021
22namespace llvm {
23
24class MCAssembler;
Aaron Ballmanbe648a32014-03-27 14:10:00 +000025struct MCFixupKindInfo;
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000026class MCObjectWriter;
Simon Atanasyan6d795862017-09-07 12:54:26 +000027class MCRegisterInfo;
28class Target;
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000029
30class MipsAsmBackend : public MCAsmBackend {
Simon Atanasyan6d795862017-09-07 12:54:26 +000031 Triple TheTriple;
Simon Atanasyan117665582017-09-21 10:44:26 +000032 bool IsN32;
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000033
34public:
Simon Atanasyan6d795862017-09-07 12:54:26 +000035 MipsAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT,
Simon Atanasyan117665582017-09-21 10:44:26 +000036 StringRef CPU, bool N32)
Peter Collingbourne571a3302018-05-21 17:57:19 +000037 : MCAsmBackend(TT.isLittleEndian() ? support::little : support::big),
38 TheTriple(TT), IsN32(N32) {}
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000039
Peter Collingbournedcd7d6c2018-05-21 19:20:29 +000040 std::unique_ptr<MCObjectTargetWriter>
41 createObjectTargetWriter() const override;
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000042
Rafael Espindola801b42d2017-06-23 22:52:36 +000043 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
44 const MCValue &Target, MutableArrayRef<char> Data,
Rafael Espindola1beb7022017-07-11 23:18:25 +000045 uint64_t Value, bool IsResolved) const override;
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000046
David Majnemerce108422016-01-19 23:05:27 +000047 Optional<MCFixupKind> getFixupKind(StringRef Name) const override;
Craig Topper56c590a2014-04-29 07:58:02 +000048 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000049
Craig Topper56c590a2014-04-29 07:58:02 +000050 unsigned getNumFixupKinds() const override {
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000051 return Mips::NumTargetFixupKinds;
52 }
53
54 /// @name Target Relaxation Interfaces
55 /// @{
56
57 /// MayNeedRelaxation - Check whether the given instruction may need
58 /// relaxation.
59 ///
60 /// \param Inst - The instruction to test.
Craig Topper56c590a2014-04-29 07:58:02 +000061 bool mayNeedRelaxation(const MCInst &Inst) const override {
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000062 return false;
63 }
64
65 /// fixupNeedsRelaxation - Target specific predicate for whether a given
66 /// fixup requires the associated instruction to be relaxed.
67 bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
68 const MCRelaxableFragment *DF,
Craig Topper56c590a2014-04-29 07:58:02 +000069 const MCAsmLayout &Layout) const override {
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000070 // FIXME.
Craig Topper35b2f752014-06-19 06:10:58 +000071 llvm_unreachable("RelaxInstruction() unimplemented");
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000072 return false;
73 }
74
75 /// RelaxInstruction - Relax the instruction in the given fragment
76 /// to the next wider instruction.
77 ///
78 /// \param Inst - The instruction to relax, which may be the same
79 /// as the output.
80 /// \param [out] Res On return, the relaxed instruction.
Nirav Dave86030622016-07-11 14:23:53 +000081 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
82 MCInst &Res) const override {}
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000083
84 /// @}
85
Peter Collingbourne571a3302018-05-21 17:57:19 +000086 bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000087
Simon Atanasyan3a44bcf2018-06-01 16:37:42 +000088 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
89 const MCValue &Target) override;
90
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000091}; // class MipsAsmBackend
92
Alexander Kornienkof00654e2015-06-23 09:49:53 +000093} // namespace
Zoran Jovanovicada38ef2014-03-27 12:38:40 +000094
95#endif