Andrew Lenharth | 3c12772 | 2005-01-24 18:45:41 +0000 | [diff] [blame^] | 1 | //===-- AlphaTargetMachine.cpp - Define TargetMachine for Alpha -----------===// |
Andrew Lenharth | a1b5ca2 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by the LLVM research group and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // |
| 11 | //===----------------------------------------------------------------------===// |
| 12 | |
| 13 | #include "Alpha.h" |
| 14 | #include "AlphaTargetMachine.h" |
Andrew Lenharth | a1b5ca2 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 15 | #include "llvm/CodeGen/Passes.h" |
| 16 | #include "llvm/Target/TargetOptions.h" |
| 17 | #include "llvm/Target/TargetMachineRegistry.h" |
| 18 | #include "llvm/Transforms/Scalar.h" |
Andrew Lenharth | a1b5ca2 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 19 | #include <iostream> |
| 20 | using namespace llvm; |
| 21 | |
| 22 | namespace { |
| 23 | // Register the targets |
| 24 | RegisterTarget<AlphaTargetMachine> X("alpha", " Alpha (incomplete)"); |
| 25 | } |
| 26 | |
| 27 | AlphaTargetMachine::AlphaTargetMachine( const Module &M, IntrinsicLowering *IL) |
| 28 | : TargetMachine("alpha", IL, true), |
| 29 | FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) //TODO: check these |
Andrew Lenharth | a1b5ca2 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 30 | {} |
| 31 | |
| 32 | bool AlphaTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM, |
| 33 | MachineCodeEmitter &MCE) |
| 34 | { |
| 35 | assert(0 && "TODO"); |
| 36 | return false; |
| 37 | } |
| 38 | |
| 39 | |
| 40 | /// addPassesToEmitAssembly - Add passes to the specified pass manager |
| 41 | /// to implement a static compiler for this target. |
| 42 | /// |
| 43 | bool AlphaTargetMachine::addPassesToEmitAssembly(PassManager &PM, |
| 44 | std::ostream &Out) { |
| 45 | |
| 46 | // FIXME: Implement efficient support for garbage collection intrinsics. |
| 47 | PM.add(createLowerGCPass()); |
| 48 | |
| 49 | // FIXME: Implement the invoke/unwind instructions! |
| 50 | PM.add(createLowerInvokePass()); |
| 51 | |
| 52 | // FIXME: Implement the switch instruction in the instruction selector! |
| 53 | PM.add(createLowerSwitchPass()); |
| 54 | |
Andrew Lenharth | a1b5ca2 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 55 | // Make sure that no unreachable blocks are instruction selected. |
| 56 | PM.add(createUnreachableBlockEliminationPass()); |
| 57 | |
| 58 | PM.add(createAlphaPatternInstructionSelector(*this)); |
| 59 | |
| 60 | if (PrintMachineCode) |
| 61 | PM.add(createMachineFunctionPrinterPass(&std::cerr)); |
| 62 | |
| 63 | PM.add(createRegisterAllocator()); |
| 64 | |
| 65 | if (PrintMachineCode) |
| 66 | PM.add(createMachineFunctionPrinterPass(&std::cerr)); |
| 67 | |
| 68 | PM.add(createPrologEpilogCodeInserter()); |
| 69 | |
| 70 | // Must run branch selection immediately preceding the asm printer |
| 71 | //PM.add(createAlphaBranchSelectionPass()); |
| 72 | |
| 73 | PM.add(createAlphaCodePrinterPass(Out, *this)); |
| 74 | |
| 75 | PM.add(createMachineCodeDeleter()); |
| 76 | return false; |
| 77 | } |