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gerrit-public.fairphone.software / toolchain / llvm-project / 3c7e276d2478238f839ab0f9d3ede33ca0bb92cd / . / llvm / test / CodeGen / PowerPC / build-vector-tests.ll
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Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]1; RUN: llc -mcpu=pwr9 -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-unknown \
2; RUN: < %s | FileCheck %s -check-prefix=P9BE -implicit-check-not frsp
3; RUN: llc -mcpu=pwr9 -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown \
4; RUN: < %s | FileCheck %s -check-prefix=P9LE -implicit-check-not frsp
5; RUN: llc -mcpu=pwr8 -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-unknown \
6; RUN: < %s | FileCheck %s -check-prefix=P8BE -implicit-check-not frsp
7; RUN: llc -mcpu=pwr8 -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown \
8; RUN: < %s | FileCheck %s -check-prefix=P8LE -implicit-check-not frsp
9
10; This test case comes from the following C test case (included as it may be
11; slightly more readable than the LLVM IR.
12
13;/* This test case provides various ways of building vectors to ensure we
14; produce optimal code for all cases. The cases are (for each type):
15; - All zeros
16; - All ones
17; - Splat of a constant
18; - From different values already in registers
19; - From different constants
20; - From different values in memory
21; - Splat of a value in register
22; - Splat of a value in memory
23; - Inserting element into existing vector
24; - Inserting element from existing vector into existing vector
25;
26; With conversions (float <-> int)
27; - Splat of a constant
28; - From different values already in registers
29; - From different constants
30; - From different values in memory
31; - Splat of a value in register
32; - Splat of a value in memory
33; - Inserting element into existing vector
34; - Inserting element from existing vector into existing vector
35;*/
36;
37;/*=================================== int ===================================*/
38;// P8: xxlxor //
39;// P9: xxlxor //
40;vector int allZeroi() { //
41; return (vector int)0; //
42;} //
43;// P8: vspltisb -1 //
44;// P9: xxspltisb 255 //
45;vector int allOnei() { //
46; return (vector int)-1; //
47;} //
48;// P8: vspltisw 1 //
49;// P9: vspltisw 1 //
50;vector int spltConst1i() { //
51; return (vector int)1; //
52;} //
53;// P8: vspltisw -15; vsrw //
54;// P9: vspltisw -15; vsrw //
55;vector int spltConst16ki() { //
56; return (vector int)((1<<15) - 1); //
57;} //
58;// P8: vspltisw -16; vsrw //
59;// P9: vspltisw -16; vsrw //
60;vector int spltConst32ki() { //
61; return (vector int)((1<<16) - 1); //
62;} //
63;// P8: 4 x mtvsrwz, 2 x xxmrgh, vmrgow //
64;// P9: 2 x mtvsrdd, vmrgow //
65;vector int fromRegsi(int a, int b, int c, int d) { //
66; return (vector int){ a, b, c, d }; //
67;} //
68;// P8: lxvd2x, xxswapd //
69;// P9: lxvx (or even lxv) //
70;vector int fromDiffConstsi() { //
71; return (vector int) { 242, -113, 889, 19 }; //
72;} //
73;// P8: lxvd2x, xxswapd //
74;// P9: lxvx //
75;vector int fromDiffMemConsAi(int *arr) { //
76; return (vector int) { arr[0], arr[1], arr[2], arr[3] }; //
77;} //
78;// P8: 2 x lxvd2x, 2 x xxswapd, vperm //
79;// P9: 2 x lxvx, vperm //
80;vector int fromDiffMemConsDi(int *arr) { //
81; return (vector int) { arr[3], arr[2], arr[1], arr[0] }; //
82;} //
83;// P8: sldi 2, lxvd2x, xxswapd //
84;// P9: sldi 2, lxvx //
85;vector int fromDiffMemVarAi(int *arr, int elem) { //
86; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; //
87;} //
88;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm //
89;// P9: sldi 2, 2 x lxvx, vperm //
90;vector int fromDiffMemVarDi(int *arr, int elem) { //
91; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; //
92;} //
93;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow //
94;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow //
95;vector int fromRandMemConsi(int *arr) { //
96; return (vector int) { arr[4], arr[18], arr[2], arr[88] }; //
97;} //
98;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow //
99;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow //
100;vector int fromRandMemVari(int *arr, int elem) { //
101; return (vector int) { arr[elem+4], arr[elem+1], arr[elem+2], arr[elem+8] };//
102;} //
103;// P8: mtvsrwz, xxspltw //
104;// P9: mtvsrws //
105;vector int spltRegVali(int val) { //
106; return (vector int) val; //
107;} //
108;// P8: lxsiwax, xxspltw //
109;// P9: lxvwsx //
110;vector int spltMemVali(int *ptr) { //
111; return (vector int)*ptr; //
112;} //
113;// P8: vspltisw //
114;// P9: vspltisw //
115;vector int spltCnstConvftoi() { //
116; return (vector int) 4.74f; //
117;} //
118;// P8: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws //
119;// P9: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvdpsxws //
120;vector int fromRegsConvftoi(float a, float b, float c, float d) { //
121; return (vector int) { a, b, c, d }; //
122;} //
123;// P8: lxvd2x, xxswapd //
124;// P9: lxvx (even lxv) //
125;vector int fromDiffConstsConvftoi() { //
126; return (vector int) { 24.46f, 234.f, 988.19f, 422.39f }; //
127;} //
128;// P8: lxvd2x, xxswapd, xvcvspsxws //
129;// P9: lxvx, xvcvspsxws //
130;vector int fromDiffMemConsAConvftoi(float *ptr) { //
131; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; //
132;} //
133;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspsxws //
134;// P9: 2 x lxvx, vperm, xvcvspsxws //
135;vector int fromDiffMemConsDConvftoi(float *ptr) { //
136; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; //
137;} //
138;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws //
139;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws //
140;// Note: if the consecutive loads learns to handle pre-inc, this can be: //
141;// sldi 2, load, xvcvspuxws //
142;vector int fromDiffMemVarAConvftoi(float *arr, int elem) { //
143; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; //
144;} //
145;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws //
146;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws //
147;// Note: if the consecutive loads learns to handle pre-inc, this can be: //
148;// sldi 2, 2 x load, vperm, xvcvspuxws //
149;vector int fromDiffMemVarDConvftoi(float *arr, int elem) { //
150; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; //
151;} //
152;// P8: xscvdpsxws, xxspltw //
153;// P9: xscvdpsxws, xxspltw //
154;vector int spltRegValConvftoi(float val) { //
155; return (vector int) val; //
156;} //
157;// P8: lxsspx, xscvdpsxws, xxspltw //
158;// P9: lxvwsx, xvcvspsxws //
159;vector int spltMemValConvftoi(float *ptr) { //
160; return (vector int)*ptr; //
161;} //
162;// P8: vspltisw //
163;// P9: vspltisw //
164;vector int spltCnstConvdtoi() { //
165; return (vector int) 4.74; //
166;} //
167;// P8: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws //
168;// P9: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws //
169;vector int fromRegsConvdtoi(double a, double b, double c, double d) { //
170; return (vector int) { a, b, c, d }; //
171;} //
172;// P8: lxvd2x, xxswapd //
173;// P9: lxvx (even lxv) //
174;vector int fromDiffConstsConvdtoi() { //
175; return (vector int) { 24.46, 234., 988.19, 422.39 }; //
176;} //
177;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvdpsp, vmrgew, //
178;// xvcvspsxws //
179;// P9: 2 x lxvx, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvdpsp, vmrgew, //
180;// xvcvspsxws //
181;vector int fromDiffMemConsAConvdtoi(double *ptr) { //
182; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; //
183;} //
184;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws //
185;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws //
186;vector int fromDiffMemConsDConvdtoi(double *ptr) { //
187; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; //
188;} //
189;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws //
190;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws //
191;vector int fromDiffMemVarAConvdtoi(double *arr, int elem) { //
192; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; //
193;} //
194;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws //
195;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws //
196;vector int fromDiffMemVarDConvdtoi(double *arr, int elem) { //
197; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; //
198;} //
199;// P8: xscvdpsxws, xxspltw //
200;// P9: xscvdpsxws, xxspltw //
201;vector int spltRegValConvdtoi(double val) { //
202; return (vector int) val; //
203;} //
204;// P8: lxsdx, xscvdpsxws, xxspltw //
205;// P9: lxssp, xscvdpsxws, xxspltw //
206;vector int spltMemValConvdtoi(double *ptr) { //
207; return (vector int)*ptr; //
208;} //
209;/*=================================== int ===================================*/
210;/*=============================== unsigned int ==============================*/
211;// P8: xxlxor //
212;// P9: xxlxor //
213;vector unsigned int allZeroui() { //
214; return (vector unsigned int)0; //
215;} //
216;// P8: vspltisb -1 //
217;// P9: xxspltisb 255 //
218;vector unsigned int allOneui() { //
219; return (vector unsigned int)-1; //
220;} //
221;// P8: vspltisw 1 //
222;// P9: vspltisw 1 //
223;vector unsigned int spltConst1ui() { //
224; return (vector unsigned int)1; //
225;} //
226;// P8: vspltisw -15; vsrw //
227;// P9: vspltisw -15; vsrw //
228;vector unsigned int spltConst16kui() { //
229; return (vector unsigned int)((1<<15) - 1); //
230;} //
231;// P8: vspltisw -16; vsrw //
232;// P9: vspltisw -16; vsrw //
233;vector unsigned int spltConst32kui() { //
234; return (vector unsigned int)((1<<16) - 1); //
235;} //
236;// P8: 4 x mtvsrwz, 2 x xxmrghd, vmrgow //
237;// P9: 2 x mtvsrdd, vmrgow //
238;vector unsigned int fromRegsui(unsigned int a, unsigned int b, //
239; unsigned int c, unsigned int d) { //
240; return (vector unsigned int){ a, b, c, d }; //
241;} //
242;// P8: lxvd2x, xxswapd //
243;// P9: lxvx (or even lxv) //
244;vector unsigned int fromDiffConstsui() { //
245; return (vector unsigned int) { 242, -113, 889, 19 }; //
246;} //
247;// P8: lxvd2x, xxswapd //
248;// P9: lxvx //
249;vector unsigned int fromDiffMemConsAui(unsigned int *arr) { //
250; return (vector unsigned int) { arr[0], arr[1], arr[2], arr[3] }; //
251;} //
252;// P8: 2 x lxvd2x, 2 x xxswapd, vperm //
253;// P9: 2 x lxvx, vperm //
254;vector unsigned int fromDiffMemConsDui(unsigned int *arr) { //
255; return (vector unsigned int) { arr[3], arr[2], arr[1], arr[0] }; //
256;} //
257;// P8: sldi 2, lxvd2x, xxswapd //
258;// P9: sldi 2, lxvx //
259;vector unsigned int fromDiffMemVarAui(unsigned int *arr, int elem) { //
260; return (vector unsigned int) { arr[elem], arr[elem+1], //
261; arr[elem+2], arr[elem+3] }; //
262;} //
263;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm //
264;// P9: sldi 2, 2 x lxvx, vperm //
265;vector unsigned int fromDiffMemVarDui(unsigned int *arr, int elem) { //
266; return (vector unsigned int) { arr[elem], arr[elem-1], //
267; arr[elem-2], arr[elem-3] }; //
268;} //
269;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow //
270;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow //
271;vector unsigned int fromRandMemConsui(unsigned int *arr) { //
272; return (vector unsigned int) { arr[4], arr[18], arr[2], arr[88] }; //
273;} //
274;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow //
275;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow //
276;vector unsigned int fromRandMemVarui(unsigned int *arr, int elem) { //
277; return (vector unsigned int) { arr[elem+4], arr[elem+1], //
278; arr[elem+2], arr[elem+8] }; //
279;} //
280;// P8: mtvsrwz, xxspltw //
281;// P9: mtvsrws //
282;vector unsigned int spltRegValui(unsigned int val) { //
283; return (vector unsigned int) val; //
284;} //
285;// P8: lxsiwax, xxspltw //
286;// P9: lxvwsx //
287;vector unsigned int spltMemValui(unsigned int *ptr) { //
288; return (vector unsigned int)*ptr; //
289;} //
290;// P8: vspltisw //
291;// P9: vspltisw //
292;vector unsigned int spltCnstConvftoui() { //
293; return (vector unsigned int) 4.74f; //
294;} //
295;// P8: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws //
296;// P9: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws //
297;vector unsigned int fromRegsConvftoui(float a, float b, float c, float d) { //
298; return (vector unsigned int) { a, b, c, d }; //
299;} //
300;// P8: lxvd2x, xxswapd //
301;// P9: lxvx (even lxv) //
302;vector unsigned int fromDiffConstsConvftoui() { //
303; return (vector unsigned int) { 24.46f, 234.f, 988.19f, 422.39f }; //
304;} //
305;// P8: lxvd2x, xxswapd, xvcvspuxws //
306;// P9: lxvx, xvcvspuxws //
307;vector unsigned int fromDiffMemConsAConvftoui(float *ptr) { //
308; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; //
309;} //
310;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspuxws //
311;// P9: 2 x lxvx, vperm, xvcvspuxws //
312;vector unsigned int fromDiffMemConsDConvftoui(float *ptr) { //
313; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; //
314;} //
315;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws //
316;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws //
317;// Note: if the consecutive loads learns to handle pre-inc, this can be: //
318;// sldi 2, load, xvcvspuxws //
319;vector unsigned int fromDiffMemVarAConvftoui(float *arr, int elem) { //
320; return (vector unsigned int) { arr[elem], arr[elem+1], //
321; arr[elem+2], arr[elem+3] }; //
322;} //
323;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws //
324;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws //
325;// Note: if the consecutive loads learns to handle pre-inc, this can be: //
326;// sldi 2, 2 x load, vperm, xvcvspuxws //
327;vector unsigned int fromDiffMemVarDConvftoui(float *arr, int elem) { //
328; return (vector unsigned int) { arr[elem], arr[elem-1], //
329; arr[elem-2], arr[elem-3] }; //
330;} //
331;// P8: xscvdpuxws, xxspltw //
332;// P9: xscvdpuxws, xxspltw //
333;vector unsigned int spltRegValConvftoui(float val) { //
334; return (vector unsigned int) val; //
335;} //
336;// P8: lxsspx, xscvdpuxws, xxspltw //
337;// P9: lxvwsx, xvcvspuxws //
338;vector unsigned int spltMemValConvftoui(float *ptr) { //
339; return (vector unsigned int)*ptr; //
340;} //
341;// P8: vspltisw //
342;// P9: vspltisw //
343;vector unsigned int spltCnstConvdtoui() { //
344; return (vector unsigned int) 4.74; //
345;} //
346;// P8: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws //
347;// P9: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws //
348;vector unsigned int fromRegsConvdtoui(double a, double b, //
349; double c, double d) { //
350; return (vector unsigned int) { a, b, c, d }; //
351;} //
352;// P8: lxvd2x, xxswapd //
353;// P9: lxvx (even lxv) //
354;vector unsigned int fromDiffConstsConvdtoui() { //
355; return (vector unsigned int) { 24.46, 234., 988.19, 422.39 }; //
356;} //
357;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvdpsp, vmrgew, //
358;// xvcvspuxws //
359;// P9: 2 x lxvx, xxmrgld, xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws //
360;vector unsigned int fromDiffMemConsAConvdtoui(double *ptr) { //
361; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; //
362;} //
363;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws //
364;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws //
365;vector unsigned int fromDiffMemConsDConvdtoui(double *ptr) { //
366; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; //
367;} //
368;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws //
369;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws //
370;vector unsigned int fromDiffMemVarAConvdtoui(double *arr, int elem) { //
371; return (vector unsigned int) { arr[elem], arr[elem+1], //
372; arr[elem+2], arr[elem+3] }; //
373;} //
374;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws //
375;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws //
376;vector unsigned int fromDiffMemVarDConvdtoui(double *arr, int elem) { //
377; return (vector unsigned int) { arr[elem], arr[elem-1], //
378; arr[elem-2], arr[elem-3] }; //
379;} //
380;// P8: xscvdpuxws, xxspltw //
381;// P9: xscvdpuxws, xxspltw //
382;vector unsigned int spltRegValConvdtoui(double val) { //
383; return (vector unsigned int) val; //
384;} //
385;// P8: lxsspx, xscvdpuxws, xxspltw //
386;// P9: lfd, xscvdpuxws, xxspltw //
387;vector unsigned int spltMemValConvdtoui(double *ptr) { //
388; return (vector unsigned int)*ptr; //
389;} //
390;/*=============================== unsigned int ==============================*/
391;/*=============================== long long =================================*/
392;// P8: xxlxor //
393;// P9: xxlxor //
394;vector long long allZeroll() { //
395; return (vector long long)0; //
396;} //
397;// P8: vspltisb -1 //
398;// P9: xxspltisb 255 //
399;vector long long allOnell() { //
400; return (vector long long)-1; //
401;} //
402;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
403;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
404;vector long long spltConst1ll() { //
405; return (vector long long)1; //
406;} //
407;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
408;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
409;vector long long spltConst16kll() { //
410; return (vector long long)((1<<15) - 1); //
411;} //
412;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
413;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
414;vector long long spltConst32kll() { //
415; return (vector long long)((1<<16) - 1); //
416;} //
417;// P8: 2 x mtvsrd, xxmrghd //
418;// P9: mtvsrdd //
419;vector long long fromRegsll(long long a, long long b) { //
420; return (vector long long){ a, b }; //
421;} //
422;// P8: lxvd2x, xxswapd //
423;// P9: lxvx (or even lxv) //
424;vector long long fromDiffConstsll() { //
425; return (vector long long) { 242, -113 }; //
426;} //
427;// P8: lxvd2x, xxswapd //
428;// P9: lxvx //
429;vector long long fromDiffMemConsAll(long long *arr) { //
430; return (vector long long) { arr[0], arr[1] }; //
431;} //
432;// P8: lxvd2x //
433;// P9: lxvx, xxswapd (maybe just use lxvd2x) //
434;vector long long fromDiffMemConsDll(long long *arr) { //
435; return (vector long long) { arr[3], arr[2] }; //
436;} //
437;// P8: sldi 3, lxvd2x, xxswapd //
438;// P9: sldi 3, lxvx //
439;vector long long fromDiffMemVarAll(long long *arr, int elem) { //
440; return (vector long long) { arr[elem], arr[elem+1] }; //
441;} //
442;// P8: sldi 3, lxvd2x //
443;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) //
444;vector long long fromDiffMemVarDll(long long *arr, int elem) { //
445; return (vector long long) { arr[elem], arr[elem-1] }; //
446;} //
447;// P8: 2 x ld, 2 x mtvsrd, xxmrghd //
448;// P9: 2 x ld, mtvsrdd //
449;vector long long fromRandMemConsll(long long *arr) { //
450; return (vector long long) { arr[4], arr[18] }; //
451;} //
452;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd //
453;// P9: sldi 3, add, 2 x ld, mtvsrdd //
454;vector long long fromRandMemVarll(long long *arr, int elem) { //
455; return (vector long long) { arr[elem+4], arr[elem+1] }; //
456;} //
457;// P8: mtvsrd, xxspltd //
458;// P9: mtvsrdd //
459;vector long long spltRegValll(long long val) { //
460; return (vector long long) val; //
461;} //
462;// P8: lxvdsx //
463;// P9: lxvdsx //
464;vector long long spltMemValll(long long *ptr) { //
465; return (vector long long)*ptr; //
466;} //
467;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
468;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
469;vector long long spltCnstConvftoll() { //
470; return (vector long long) 4.74f; //
471;} //
472;// P8: xxmrghd, xvcvdpsxds //
473;// P9: xxmrghd, xvcvdpsxds //
474;vector long long fromRegsConvftoll(float a, float b) { //
475; return (vector long long) { a, b }; //
476;} //
477;// P8: lxvd2x, xxswapd //
478;// P9: lxvx (even lxv) //
479;vector long long fromDiffConstsConvftoll() { //
480; return (vector long long) { 24.46f, 234.f }; //
481;} //
482;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds //
483;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds //
484;vector long long fromDiffMemConsAConvftoll(float *ptr) { //
485; return (vector long long) { ptr[0], ptr[1] }; //
486;} //
487;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds //
488;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds //
489;vector long long fromDiffMemConsDConvftoll(float *ptr) { //
490; return (vector long long) { ptr[3], ptr[2] }; //
491;} //
492;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds //
493;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds //
494;vector long long fromDiffMemVarAConvftoll(float *arr, int elem) { //
495; return (vector long long) { arr[elem], arr[elem+1] }; //
496;} //
497;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds //
498;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds //
499;vector long long fromDiffMemVarDConvftoll(float *arr, int elem) { //
500; return (vector long long) { arr[elem], arr[elem-1] }; //
501;} //
502;// P8: xscvdpsxds, xxspltd //
503;// P9: xscvdpsxds, xxspltd //
504;vector long long spltRegValConvftoll(float val) { //
505; return (vector long long) val; //
506;} //
507;// P8: lxsspx, xscvdpsxds, xxspltd //
508;// P9: lfs, xscvdpsxds, xxspltd //
509;vector long long spltMemValConvftoll(float *ptr) { //
510; return (vector long long)*ptr; //
511;} //
512;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
513;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
514;vector long long spltCnstConvdtoll() { //
515; return (vector long long) 4.74; //
516;} //
517;// P8: xxmrghd, xvcvdpsxds //
518;// P9: xxmrghd, xvcvdpsxds //
519;vector long long fromRegsConvdtoll(double a, double b) { //
520; return (vector long long) { a, b }; //
521;} //
522;// P8: lxvd2x, xxswapd //
523;// P9: lxvx (even lxv) //
524;vector long long fromDiffConstsConvdtoll() { //
525; return (vector long long) { 24.46, 234. }; //
526;} //
527;// P8: lxvd2x, xxswapd, xvcvdpsxds //
528;// P9: lxvx, xvcvdpsxds //
529;vector long long fromDiffMemConsAConvdtoll(double *ptr) { //
530; return (vector long long) { ptr[0], ptr[1] }; //
531;} //
532;// P8: lxvd2x, xvcvdpsxds //
533;// P9: lxvx, xxswapd, xvcvdpsxds //
534;vector long long fromDiffMemConsDConvdtoll(double *ptr) { //
535; return (vector long long) { ptr[3], ptr[2] }; //
536;} //
537;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpsxds //
538;// P9: sldi 3, lxvx, xvcvdpsxds //
539;vector long long fromDiffMemVarAConvdtoll(double *arr, int elem) { //
540; return (vector long long) { arr[elem], arr[elem+1] }; //
541;} //
542;// P8: sldi 3, lxvd2x, xvcvdpsxds //
543;// P9: sldi 3, lxvx, xxswapd, xvcvdpsxds //
544;vector long long fromDiffMemVarDConvdtoll(double *arr, int elem) { //
545; return (vector long long) { arr[elem], arr[elem-1] }; //
546;} //
547;// P8: xscvdpsxds, xxspltd //
548;// P9: xscvdpsxds, xxspltd //
549;vector long long spltRegValConvdtoll(double val) { //
550; return (vector long long) val; //
551;} //
552;// P8: lxvdsx, xvcvdpsxds //
553;// P9: lxvdsx, xvcvdpsxds //
554;vector long long spltMemValConvdtoll(double *ptr) { //
555; return (vector long long)*ptr; //
556;} //
557;/*=============================== long long =================================*/
558;/*========================== unsigned long long =============================*/
559;// P8: xxlxor //
560;// P9: xxlxor //
561;vector unsigned long long allZeroull() { //
562; return (vector unsigned long long)0; //
563;} //
564;// P8: vspltisb -1 //
565;// P9: xxspltisb 255 //
566;vector unsigned long long allOneull() { //
567; return (vector unsigned long long)-1; //
568;} //
569;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
570;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
571;vector unsigned long long spltConst1ull() { //
572; return (vector unsigned long long)1; //
573;} //
574;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
575;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
576;vector unsigned long long spltConst16kull() { //
577; return (vector unsigned long long)((1<<15) - 1); //
578;} //
579;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
580;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
581;vector unsigned long long spltConst32kull() { //
582; return (vector unsigned long long)((1<<16) - 1); //
583;} //
584;// P8: 2 x mtvsrd, xxmrghd //
585;// P9: mtvsrdd //
586;vector unsigned long long fromRegsull(unsigned long long a, //
587; unsigned long long b) { //
588; return (vector unsigned long long){ a, b }; //
589;} //
590;// P8: lxvd2x, xxswapd //
591;// P9: lxvx (or even lxv) //
592;vector unsigned long long fromDiffConstsull() { //
593; return (vector unsigned long long) { 242, -113 }; //
594;} //
595;// P8: lxvd2x, xxswapd //
596;// P9: lxvx //
597;vector unsigned long long fromDiffMemConsAull(unsigned long long *arr) { //
598; return (vector unsigned long long) { arr[0], arr[1] }; //
599;} //
600;// P8: lxvd2x //
601;// P9: lxvx, xxswapd (maybe just use lxvd2x) //
602;vector unsigned long long fromDiffMemConsDull(unsigned long long *arr) { //
603; return (vector unsigned long long) { arr[3], arr[2] }; //
604;} //
605;// P8: sldi 3, lxvd2x, xxswapd //
606;// P9: sldi 3, lxvx //
607;vector unsigned long long fromDiffMemVarAull(unsigned long long *arr, //
608; int elem) { //
609; return (vector unsigned long long) { arr[elem], arr[elem+1] }; //
610;} //
611;// P8: sldi 3, lxvd2x //
612;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) //
613;vector unsigned long long fromDiffMemVarDull(unsigned long long *arr, //
614; int elem) { //
615; return (vector unsigned long long) { arr[elem], arr[elem-1] }; //
616;} //
617;// P8: 2 x ld, 2 x mtvsrd, xxmrghd //
618;// P9: 2 x ld, mtvsrdd //
619;vector unsigned long long fromRandMemConsull(unsigned long long *arr) { //
620; return (vector unsigned long long) { arr[4], arr[18] }; //
621;} //
622;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd //
623;// P9: sldi 3, add, 2 x ld, mtvsrdd //
624;vector unsigned long long fromRandMemVarull(unsigned long long *arr, //
625; int elem) { //
626; return (vector unsigned long long) { arr[elem+4], arr[elem+1] }; //
627;} //
628;// P8: mtvsrd, xxspltd //
629;// P9: mtvsrdd //
630;vector unsigned long long spltRegValull(unsigned long long val) { //
631; return (vector unsigned long long) val; //
632;} //
633;// P8: lxvdsx //
634;// P9: lxvdsx //
635;vector unsigned long long spltMemValull(unsigned long long *ptr) { //
636; return (vector unsigned long long)*ptr; //
637;} //
638;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
639;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
640;vector unsigned long long spltCnstConvftoull() { //
641; return (vector unsigned long long) 4.74f; //
642;} //
643;// P8: xxmrghd, xvcvdpuxds //
644;// P9: xxmrghd, xvcvdpuxds //
645;vector unsigned long long fromRegsConvftoull(float a, float b) { //
646; return (vector unsigned long long) { a, b }; //
647;} //
648;// P8: lxvd2x, xxswapd //
649;// P9: lxvx (even lxv) //
650;vector unsigned long long fromDiffConstsConvftoull() { //
651; return (vector unsigned long long) { 24.46f, 234.f }; //
652;} //
653;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds //
654;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds //
655;vector unsigned long long fromDiffMemConsAConvftoull(float *ptr) { //
656; return (vector unsigned long long) { ptr[0], ptr[1] }; //
657;} //
658;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds //
659;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds //
660;vector unsigned long long fromDiffMemConsDConvftoull(float *ptr) { //
661; return (vector unsigned long long) { ptr[3], ptr[2] }; //
662;} //
663;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds //
664;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds //
665;vector unsigned long long fromDiffMemVarAConvftoull(float *arr, int elem) { //
666; return (vector unsigned long long) { arr[elem], arr[elem+1] }; //
667;} //
668;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds //
669;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds //
670;vector unsigned long long fromDiffMemVarDConvftoull(float *arr, int elem) { //
671; return (vector unsigned long long) { arr[elem], arr[elem-1] }; //
672;} //
673;// P8: xscvdpuxds, xxspltd //
674;// P9: xscvdpuxds, xxspltd //
675;vector unsigned long long spltRegValConvftoull(float val) { //
676; return (vector unsigned long long) val; //
677;} //
678;// P8: lxsspx, xscvdpuxds, xxspltd //
679;// P9: lfs, xscvdpuxds, xxspltd //
680;vector unsigned long long spltMemValConvftoull(float *ptr) { //
681; return (vector unsigned long long)*ptr; //
682;} //
683;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
684;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
685;vector unsigned long long spltCnstConvdtoull() { //
686; return (vector unsigned long long) 4.74; //
687;} //
688;// P8: xxmrghd, xvcvdpuxds //
689;// P9: xxmrghd, xvcvdpuxds //
690;vector unsigned long long fromRegsConvdtoull(double a, double b) { //
691; return (vector unsigned long long) { a, b }; //
692;} //
693;// P8: lxvd2x, xxswapd //
694;// P9: lxvx (even lxv) //
695;vector unsigned long long fromDiffConstsConvdtoull() { //
696; return (vector unsigned long long) { 24.46, 234. }; //
697;} //
698;// P8: lxvd2x, xxswapd, xvcvdpuxds //
699;// P9: lxvx, xvcvdpuxds //
700;vector unsigned long long fromDiffMemConsAConvdtoull(double *ptr) { //
701; return (vector unsigned long long) { ptr[0], ptr[1] }; //
702;} //
703;// P8: lxvd2x, xvcvdpuxds //
704;// P9: lxvx, xxswapd, xvcvdpuxds //
705;vector unsigned long long fromDiffMemConsDConvdtoull(double *ptr) { //
706; return (vector unsigned long long) { ptr[3], ptr[2] }; //
707;} //
708;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpuxds //
709;// P9: sldi 3, lxvx, xvcvdpuxds //
710;vector unsigned long long fromDiffMemVarAConvdtoull(double *arr, int elem) { //
711; return (vector unsigned long long) { arr[elem], arr[elem+1] }; //
712;} //
713;// P8: sldi 3, lxvd2x, xvcvdpuxds //
714;// P9: sldi 3, lxvx, xxswapd, xvcvdpuxds //
715;vector unsigned long long fromDiffMemVarDConvdtoull(double *arr, int elem) { //
716; return (vector unsigned long long) { arr[elem], arr[elem-1] }; //
717;} //
718;// P8: xscvdpuxds, xxspltd //
719;// P9: xscvdpuxds, xxspltd //
720;vector unsigned long long spltRegValConvdtoull(double val) { //
721; return (vector unsigned long long) val; //
722;} //
723;// P8: lxvdsx, xvcvdpuxds //
724;// P9: lxvdsx, xvcvdpuxds //
725;vector unsigned long long spltMemValConvdtoull(double *ptr) { //
726; return (vector unsigned long long)*ptr; //
727;} //
728;/*========================== unsigned long long ==============================*/
729
730; Function Attrs: norecurse nounwind readnone
731define <4 x i32> @allZeroi() {
732entry:
733 ret <4 x i32> zeroinitializer
734; P9BE-LABEL: allZeroi
735; P9LE-LABEL: allZeroi
736; P8BE-LABEL: allZeroi
737; P8LE-LABEL: allZeroi
738; P9BE: xxlxor v2, v2, v2
739; P9BE: blr
740; P9LE: xxlxor v2, v2, v2
741; P9LE: blr
742; P8BE: xxlxor v2, v2, v2
743; P8BE: blr
744; P8LE: xxlxor v2, v2, v2
745; P8LE: blr
746}
747
748; Function Attrs: norecurse nounwind readnone
749define <4 x i32> @allOnei() {
750entry:
751 ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
752; P9BE-LABEL: allOnei
753; P9LE-LABEL: allOnei
754; P8BE-LABEL: allOnei
755; P8LE-LABEL: allOnei
756; P9BE: xxspltib v2, 255
757; P9BE: blr
758; P9LE: xxspltib v2, 255
759; P9LE: blr
760; P8BE: vspltisb v2, -1
761; P8BE: blr
762; P8LE: vspltisb v2, -1
763; P8LE: blr
764}
765
766; Function Attrs: norecurse nounwind readnone
767define <4 x i32> @spltConst1i() {
768entry:
769 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1>
770; P9BE-LABEL: spltConst1i
771; P9LE-LABEL: spltConst1i
772; P8BE-LABEL: spltConst1i
773; P8LE-LABEL: spltConst1i
774; P9BE: vspltisw v2, 1
775; P9BE: blr
776; P9LE: vspltisw v2, 1
777; P9LE: blr
778; P8BE: vspltisw v2, 1
779; P8BE: blr
780; P8LE: vspltisw v2, 1
781; P8LE: blr
782}
783
784; Function Attrs: norecurse nounwind readnone
785define <4 x i32> @spltConst16ki() {
786entry:
787 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>
788; P9BE-LABEL: spltConst16ki
789; P9LE-LABEL: spltConst16ki
790; P8BE-LABEL: spltConst16ki
791; P8LE-LABEL: spltConst16ki
792; P9BE: vspltisw v2, -15
793; P9BE: vsrw v2, v2, v2
794; P9BE: blr
795; P9LE: vspltisw v2, -15
796; P9LE: vsrw v2, v2, v2
797; P9LE: blr
798; P8BE: vspltisw v2, -15
799; P8BE: vsrw v2, v2, v2
800; P8BE: blr
801; P8LE: vspltisw v2, -15
802; P8LE: vsrw v2, v2, v2
803; P8LE: blr
804}
805
806; Function Attrs: norecurse nounwind readnone
807define <4 x i32> @spltConst32ki() {
808entry:
809 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
810; P9BE-LABEL: spltConst32ki
811; P9LE-LABEL: spltConst32ki
812; P8BE-LABEL: spltConst32ki
813; P8LE-LABEL: spltConst32ki
814; P9BE: vspltisw v2, -16
815; P9BE: vsrw v2, v2, v2
816; P9BE: blr
817; P9LE: vspltisw v2, -16
818; P9LE: vsrw v2, v2, v2
819; P9LE: blr
820; P8BE: vspltisw v2, -16
821; P8BE: vsrw v2, v2, v2
822; P8BE: blr
823; P8LE: vspltisw v2, -16
824; P8LE: vsrw v2, v2, v2
825; P8LE: blr
826}
827
828; Function Attrs: norecurse nounwind readnone
829define <4 x i32> @fromRegsi(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) {
830entry:
831 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0
832 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1
833 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2
834 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3
835 ret <4 x i32> %vecinit3
836; P9BE-LABEL: fromRegsi
837; P9LE-LABEL: fromRegsi
838; P8BE-LABEL: fromRegsi
839; P8LE-LABEL: fromRegsi
840; P9BE-DAG: mtvsrdd [[REG1:v[0-9]+]], r3, r5
841; P9BE-DAG: mtvsrdd [[REG2:v[0-9]+]], r4, r6
842; P9BE: vmrgow v2, [[REG1]], [[REG2]]
843; P9BE: blr
844; P9LE-DAG: mtvsrdd [[REG1:v[0-9]+]], r5, r3
845; P9LE-DAG: mtvsrdd [[REG2:v[0-9]+]], r6, r4
846; P9LE: vmrgow v2, [[REG2]], [[REG1]]
847; P9LE: blr
848; P8BE-DAG: mtvsrwz {{[vf]}}[[REG1:[0-9]+]], r3
849; P8BE-DAG: mtvsrwz {{[vf]}}[[REG2:[0-9]+]], r4
850; P8BE-DAG: mtvsrwz {{[vf]}}[[REG3:[0-9]+]], r5
851; P8BE-DAG: mtvsrwz {{[vf]}}[[REG4:[0-9]+]], r6
852; P8BE-DAG: xxmrghd [[REG5:v[0-9]+]], {{[v][s]*}}[[REG1]], {{[v][s]*}}[[REG3]]
853; P8BE-DAG: xxmrghd [[REG6:v[0-9]+]], {{[v][s]*}}[[REG2]], {{[v][s]*}}[[REG4]]
854; P8BE: vmrgow v2, [[REG5]], [[REG6]]
855; P8LE-DAG: mtvsrwz {{[vf]}}[[REG1:[0-9]+]], r3
856; P8LE-DAG: mtvsrwz {{[vf]}}[[REG2:[0-9]+]], r4
857; P8LE-DAG: mtvsrwz {{[vf]}}[[REG3:[0-9]+]], r5
858; P8LE-DAG: mtvsrwz {{[vf]}}[[REG4:[0-9]+]], r6
859; P8LE: xxmrghd [[REG5:v[0-9]+]], {{[v][s]*}}[[REG3]], {{[v][s]*}}[[REG1]]
860; P8LE: xxmrghd [[REG6:v[0-9]+]], {{[v][s]*}}[[REG4]], {{[v][s]*}}[[REG2]]
861; P8LE: vmrgow v2, [[REG6]], [[REG5]]
862}
863
864; Function Attrs: norecurse nounwind readnone
865define <4 x i32> @fromDiffConstsi() {
866entry:
867 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19>
868; P9BE-LABEL: fromDiffConstsi
869; P9LE-LABEL: fromDiffConstsi
870; P8BE-LABEL: fromDiffConstsi
871; P8LE-LABEL: fromDiffConstsi
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]872; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]873; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]874; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]875; P9LE: blr
876; P8BE: lxvw4x
877; P8BE: blr
Nemanja Ivanovicb89c27f2017-05-02 01:47:34 +0000[diff] [blame]878; P8LE: lvx
879; P8LE-NOT: xxswapd
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]880; P8LE: blr
881}
882
883; Function Attrs: norecurse nounwind readonly
884define <4 x i32> @fromDiffMemConsAi(i32* nocapture readonly %arr) {
885entry:
886 %0 = load i32, i32* %arr, align 4
887 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
888 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 1
889 %1 = load i32, i32* %arrayidx1, align 4
890 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
891 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2
892 %2 = load i32, i32* %arrayidx3, align 4
893 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2
894 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 3
895 %3 = load i32, i32* %arrayidx5, align 4
896 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3
897 ret <4 x i32> %vecinit6
898; P9BE-LABEL: fromDiffMemConsAi
899; P9LE-LABEL: fromDiffMemConsAi
900; P8BE-LABEL: fromDiffMemConsAi
901; P8LE-LABEL: fromDiffMemConsAi
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]902; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]903; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]904; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]905; P9LE: blr
906; P8BE: lxvw4x
907; P8BE: blr
908; P8LE: lxvd2x
909; P8LE: xxswapd
910; P8LE: blr
911}
912
913; Function Attrs: norecurse nounwind readonly
914define <4 x i32> @fromDiffMemConsDi(i32* nocapture readonly %arr) {
915entry:
916 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 3
917 %0 = load i32, i32* %arrayidx, align 4
918 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
919 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2
920 %1 = load i32, i32* %arrayidx1, align 4
921 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
922 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 1
923 %2 = load i32, i32* %arrayidx3, align 4
924 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2
925 %3 = load i32, i32* %arr, align 4
926 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3
927 ret <4 x i32> %vecinit6
928; P9BE-LABEL: fromDiffMemConsDi
929; P9LE-LABEL: fromDiffMemConsDi
930; P8BE-LABEL: fromDiffMemConsDi
931; P8LE-LABEL: fromDiffMemConsDi
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]932; P9BE: lxv
933; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]934; P9BE: vperm
935; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]936; P9LE: lxv
937; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]938; P9LE: vperm
939; P9LE: blr
940; P8BE: lxvw4x
941; P8BE: lxvw4x
942; P8BE: vperm
943; P8BE: blr
944; P8LE: lxvd2x
Nemanja Ivanovicb89c27f2017-05-02 01:47:34 +0000[diff] [blame]945; P8LE-DAG: lvx
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]946; P8LE: xxswapd
947; P8LE: vperm
948; P8LE: blr
949}
950
951; Function Attrs: norecurse nounwind readonly
952define <4 x i32> @fromDiffMemVarAi(i32* nocapture readonly %arr, i32 signext %elem) {
953entry:
954 %idxprom = sext i32 %elem to i64
955 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom
956 %0 = load i32, i32* %arrayidx, align 4
957 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
958 %add = add nsw i32 %elem, 1
959 %idxprom1 = sext i32 %add to i64
960 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1
961 %1 = load i32, i32* %arrayidx2, align 4
962 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
963 %add4 = add nsw i32 %elem, 2
964 %idxprom5 = sext i32 %add4 to i64
965 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5
966 %2 = load i32, i32* %arrayidx6, align 4
967 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2
968 %add8 = add nsw i32 %elem, 3
969 %idxprom9 = sext i32 %add8 to i64
970 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9
971 %3 = load i32, i32* %arrayidx10, align 4
972 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3
973 ret <4 x i32> %vecinit11
974; P9BE-LABEL: fromDiffMemVarAi
975; P9LE-LABEL: fromDiffMemVarAi
976; P8BE-LABEL: fromDiffMemVarAi
977; P8LE-LABEL: fromDiffMemVarAi
978; P9BE: sldi r4, r4, 2
979; P9BE: lxvx v2, r3, r4
980; P9BE: blr
981; P9LE: sldi r4, r4, 2
982; P9LE: lxvx v2, r3, r4
983; P9LE: blr
984; P8BE: sldi r4, r4, 2
985; P8BE: lxvw4x {{[vs0-9]+}}, r3, r4
986; P8BE: blr
987; P8LE: sldi r4, r4, 2
988; P8LE: lxvd2x {{[vs0-9]+}}, r3, r4
989; P8LE: xxswapd
990; P8LE: blr
991}
992
993; Function Attrs: norecurse nounwind readonly
994define <4 x i32> @fromDiffMemVarDi(i32* nocapture readonly %arr, i32 signext %elem) {
995entry:
996 %idxprom = sext i32 %elem to i64
997 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom
998 %0 = load i32, i32* %arrayidx, align 4
999 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
1000 %sub = add nsw i32 %elem, -1
1001 %idxprom1 = sext i32 %sub to i64
1002 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1
1003 %1 = load i32, i32* %arrayidx2, align 4
1004 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
1005 %sub4 = add nsw i32 %elem, -2
1006 %idxprom5 = sext i32 %sub4 to i64
1007 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5
1008 %2 = load i32, i32* %arrayidx6, align 4
1009 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2
1010 %sub8 = add nsw i32 %elem, -3
1011 %idxprom9 = sext i32 %sub8 to i64
1012 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9
1013 %3 = load i32, i32* %arrayidx10, align 4
1014 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3
1015 ret <4 x i32> %vecinit11
1016; P9BE-LABEL: fromDiffMemVarDi
1017; P9LE-LABEL: fromDiffMemVarDi
1018; P8BE-LABEL: fromDiffMemVarDi
1019; P8LE-LABEL: fromDiffMemVarDi
Ehsan Amiri741b3872016-12-16 00:33:07 +0000[diff] [blame]1020; P9BE: sldi {{r[0-9]+}}, r4, 2
Nemanja Ivanovic3c7e276d2017-07-13 18:17:10 +0000[diff] [blame^]1021; P9BE-DAG: lxvx {{v[0-9]+}}
1022; P9BE-DAG: lxvx
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]1023; P9BE: vperm
1024; P9BE: blr
Ehsan Amiri741b3872016-12-16 00:33:07 +0000[diff] [blame]1025; P9LE: sldi {{r[0-9]+}}, r4, 2
Nemanja Ivanovic3c7e276d2017-07-13 18:17:10 +0000[diff] [blame^]1026; P9LE-DAG: lxvx {{v[0-9]+}}
1027; P9LE-DAG: lxvx
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]1028; P9LE: vperm
1029; P9LE: blr
Ehsan Amiri741b3872016-12-16 00:33:07 +0000[diff] [blame]1030; P8BE: sldi {{r[0-9]+}}, r4, 2
Lei Huang168d14b2017-07-10 16:44:45 +0000[diff] [blame]1031; P8BE-DAG: lxvw4x {{v[0-9]+}}, 0, r3
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]1032; P8BE-DAG: lxvw4x
1033; P8BE: vperm
1034; P8BE: blr
Ehsan Amiri741b3872016-12-16 00:33:07 +0000[diff] [blame]1035; P8LE: sldi {{r[0-9]+}}, r4, 2
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]1036; P8LE-DAG: lxvd2x
1037; P8LE-DAG: lxvd2x
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]1038; P8LE: xxswapd
1039; P8LE: vperm
1040; P8LE: blr
1041}
1042
1043; Function Attrs: norecurse nounwind readonly
1044define <4 x i32> @fromRandMemConsi(i32* nocapture readonly %arr) {
1045entry:
1046 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 4
1047 %0 = load i32, i32* %arrayidx, align 4
1048 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
1049 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 18
1050 %1 = load i32, i32* %arrayidx1, align 4
1051 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
1052 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2
1053 %2 = load i32, i32* %arrayidx3, align 4
1054 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2
1055 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 88
1056 %3 = load i32, i32* %arrayidx5, align 4
1057 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3
1058 ret <4 x i32> %vecinit6
1059; P9BE-LABEL: fromRandMemConsi
1060; P9LE-LABEL: fromRandMemConsi
1061; P8BE-LABEL: fromRandMemConsi
1062; P8LE-LABEL: fromRandMemConsi
1063; P9BE: lwz
1064; P9BE: lwz
1065; P9BE: lwz
1066; P9BE: lwz
1067; P9BE: mtvsrdd
1068; P9BE: mtvsrdd
1069; P9BE: vmrgow
1070; P9LE: lwz
1071; P9LE: lwz
1072; P9LE: lwz
1073; P9LE: lwz
1074; P9LE: mtvsrdd
1075; P9LE: mtvsrdd
1076; P9LE: vmrgow
1077; P8BE: lwz
1078; P8BE: lwz
1079; P8BE: lwz
1080; P8BE: lwz
1081; P8BE: mtvsrwz
1082; P8BE: mtvsrwz
1083; P8BE: mtvsrwz
1084; P8BE: mtvsrwz
1085; P8BE: xxmrghd
1086; P8BE: xxmrghd
1087; P8BE: vmrgow
1088; P8LE: lwz
1089; P8LE: lwz
1090; P8LE: lwz
1091; P8LE: lwz
1092; P8LE: mtvsrwz
1093; P8LE: mtvsrwz
1094; P8LE: mtvsrwz
1095; P8LE: mtvsrwz
1096; P8LE: xxmrghd
1097; P8LE: xxmrghd
1098; P8LE: vmrgow
1099}
1100
1101; Function Attrs: norecurse nounwind readonly
1102define <4 x i32> @fromRandMemVari(i32* nocapture readonly %arr, i32 signext %elem) {
1103entry:
1104 %add = add nsw i32 %elem, 4
1105 %idxprom = sext i32 %add to i64
1106 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom
1107 %0 = load i32, i32* %arrayidx, align 4
1108 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
1109 %add1 = add nsw i32 %elem, 1
1110 %idxprom2 = sext i32 %add1 to i64
1111 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 %idxprom2
1112 %1 = load i32, i32* %arrayidx3, align 4
1113 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
1114 %add5 = add nsw i32 %elem, 2
1115 %idxprom6 = sext i32 %add5 to i64
1116 %arrayidx7 = getelementptr inbounds i32, i32* %arr, i64 %idxprom6
1117 %2 = load i32, i32* %arrayidx7, align 4
1118 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2
1119 %add9 = add nsw i32 %elem, 8
1120 %idxprom10 = sext i32 %add9 to i64
1121 %arrayidx11 = getelementptr inbounds i32, i32* %arr, i64 %idxprom10
1122 %3 = load i32, i32* %arrayidx11, align 4
1123 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3
1124 ret <4 x i32> %vecinit12
1125; P9BE-LABEL: fromRandMemVari
1126; P9LE-LABEL: fromRandMemVari
1127; P8BE-LABEL: fromRandMemVari
1128; P8LE-LABEL: fromRandMemVari
1129; P9BE: sldi r4, r4, 2
1130; P9BE: lwz
1131; P9BE: lwz
1132; P9BE: lwz
1133; P9BE: lwz
1134; P9BE: mtvsrdd
1135; P9BE: mtvsrdd
1136; P9BE: vmrgow
1137; P9LE: sldi r4, r4, 2
1138; P9LE: lwz
1139; P9LE: lwz
1140; P9LE: lwz
1141; P9LE: lwz
1142; P9LE: mtvsrdd
1143; P9LE: mtvsrdd
1144; P9LE: vmrgow
1145; P8BE: sldi r4, r4, 2
1146; P8BE: lwz
1147; P8BE: lwz
1148; P8BE: lwz
1149; P8BE: lwz
1150; P8BE: mtvsrwz
1151; P8BE: mtvsrwz
1152; P8BE: mtvsrwz
1153; P8BE: mtvsrwz
1154; P8BE: xxmrghd
1155; P8BE: xxmrghd
1156; P8BE: vmrgow
1157; P8LE: sldi r4, r4, 2
1158; P8LE: lwz
1159; P8LE: lwz
1160; P8LE: lwz
1161; P8LE: lwz
1162; P8LE: mtvsrwz
1163; P8LE: mtvsrwz
1164; P8LE: mtvsrwz
1165; P8LE: mtvsrwz
1166; P8LE: xxmrghd
1167; P8LE: xxmrghd
1168; P8LE: vmrgow
1169}
1170
1171; Function Attrs: norecurse nounwind readnone
1172define <4 x i32> @spltRegVali(i32 signext %val) {
1173entry:
1174 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0
1175 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
1176 ret <4 x i32> %splat.splat
1177; P9BE-LABEL: spltRegVali
1178; P9LE-LABEL: spltRegVali
1179; P8BE-LABEL: spltRegVali
1180; P8LE-LABEL: spltRegVali
1181; P9BE: mtvsrws v2, r3
1182; P9BE: blr
1183; P9LE: mtvsrws v2, r3
1184; P9LE: blr
1185; P8BE: mtvsrwz {{[vsf0-9]+}}, r3
1186; P8BE: xxspltw v2, {{[vsf0-9]+}}, 1
1187; P8BE: blr
1188; P8LE: mtvsrwz {{[vsf0-9]+}}, r3
1189; P8LE: xxspltw v2, {{[vsf0-9]+}}, 1
1190; P8LE: blr
1191}
1192
1193; Function Attrs: norecurse nounwind readonly
1194define <4 x i32> @spltMemVali(i32* nocapture readonly %ptr) {
1195entry:
1196 %0 = load i32, i32* %ptr, align 4
1197 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0
1198 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
1199 ret <4 x i32> %splat.splat
1200; P9BE-LABEL: spltMemVali
1201; P9LE-LABEL: spltMemVali
1202; P8BE-LABEL: spltMemVali
1203; P8LE-LABEL: spltMemVali
1204; P9BE: lxvwsx v2, 0, r3
1205; P9BE: blr
1206; P9LE: lxvwsx v2, 0, r3
1207; P9LE: blr
1208; P8BE: lxsiwax {{[vsf0-9]+}}, 0, r3
1209; P8BE: xxspltw v2, {{[vsf0-9]+}}, 1
1210; P8BE: blr
1211; P8LE: lxsiwax {{[vsf0-9]+}}, 0, r3
1212; P8LE: xxspltw v2, {{[vsf0-9]+}}, 1
1213; P8LE: blr
1214}
1215
1216; Function Attrs: norecurse nounwind readnone
1217define <4 x i32> @spltCnstConvftoi() {
1218entry:
1219 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4>
1220; P9BE-LABEL: spltCnstConvftoi
1221; P9LE-LABEL: spltCnstConvftoi
1222; P8BE-LABEL: spltCnstConvftoi
1223; P8LE-LABEL: spltCnstConvftoi
1224; P9BE: vspltisw v2, 4
1225; P9BE: blr
1226; P9LE: vspltisw v2, 4
1227; P9LE: blr
1228; P8BE: vspltisw v2, 4
1229; P8BE: blr
1230; P8LE: vspltisw v2, 4
1231; P8LE: blr
1232}
1233
1234; Function Attrs: norecurse nounwind readnone
1235define <4 x i32> @fromRegsConvftoi(float %a, float %b, float %c, float %d) {
1236entry:
1237 %conv = fptosi float %a to i32
1238 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
1239 %conv1 = fptosi float %b to i32
1240 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1
1241 %conv3 = fptosi float %c to i32
1242 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2
1243 %conv5 = fptosi float %d to i32
1244 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3
1245 ret <4 x i32> %vecinit6
1246; P9BE-LABEL: fromRegsConvftoi
1247; P9LE-LABEL: fromRegsConvftoi
1248; P8BE-LABEL: fromRegsConvftoi
1249; P8LE-LABEL: fromRegsConvftoi
1250; P9BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3
1251; P9BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4
1252; P9BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
1253; P9BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
1254; P9BE: vmrgew v2, [[REG3]], [[REG4]]
1255; P9BE: xvcvspsxws v2, v2
1256; P9LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1
1257; P9LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2
1258; P9LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
1259; P9LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
1260; P9LE: vmrgew v2, [[REG4]], [[REG3]]
1261; P9LE: xvcvspsxws v2, v2
1262; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3
1263; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4
1264; P8BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
1265; P8BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
1266; P8BE: vmrgew v2, [[REG3]], [[REG4]]
1267; P8BE: xvcvspsxws v2, v2
1268; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1
1269; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2
1270; P8LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
1271; P8LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
1272; P8LE: vmrgew v2, [[REG4]], [[REG3]]
1273; P8LE: xvcvspsxws v2, v2
1274}
1275
1276; Function Attrs: norecurse nounwind readnone
1277define <4 x i32> @fromDiffConstsConvftoi() {
1278entry:
1279 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422>
1280; P9BE-LABEL: fromDiffConstsConvftoi
1281; P9LE-LABEL: fromDiffConstsConvftoi
1282; P8BE-LABEL: fromDiffConstsConvftoi
1283; P8LE-LABEL: fromDiffConstsConvftoi
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]1284; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]1285; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]1286; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]1287; P9LE: blr
1288; P8BE: lxvw4x
1289; P8BE: blr
Nemanja Ivanovicb89c27f2017-05-02 01:47:34 +0000[diff] [blame]1290; P8LE: lvx
1291; P8LE-NOT: xxswapd
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]1292; P8LE: blr
1293}
1294
1295; Function Attrs: norecurse nounwind readonly
1296define <4 x i32> @fromDiffMemConsAConvftoi(float* nocapture readonly %ptr) {
1297entry:
1298 %0 = bitcast float* %ptr to <4 x float>*
1299 %1 = load <4 x float>, <4 x float>* %0, align 4
1300 %2 = fptosi <4 x float> %1 to <4 x i32>
1301 ret <4 x i32> %2
1302; P9BE-LABEL: fromDiffMemConsAConvftoi
1303; P9LE-LABEL: fromDiffMemConsAConvftoi
1304; P8BE-LABEL: fromDiffMemConsAConvftoi
1305; P8LE-LABEL: fromDiffMemConsAConvftoi
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]1306; P9BE: lxv [[REG1:[vs0-9]+]], 0(r3)
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]1307; P9BE: xvcvspsxws v2, [[REG1]]
1308; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]1309; P9LE: lxv [[REG1:[vs0-9]+]], 0(r3)
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]1310; P9LE: xvcvspsxws v2, [[REG1]]
1311; P9LE: blr
1312; P8BE: lxvw4x [[REG1:[vs0-9]+]], 0, r3
1313; P8BE: xvcvspsxws v2, [[REG1]]
1314; P8BE: blr
1315; P8LE: lxvd2x [[REG1:[vs0-9]+]], 0, r3
Nemanja Ivanovicb89c27f2017-05-02 01:47:34 +0000[diff] [blame]1316; P8LE: xxswapd
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]1317; P8LE: xvcvspsxws v2, v2
1318; P8LE: blr
1319}
1320
1321; Function Attrs: norecurse nounwind readonly
1322define <4 x i32> @fromDiffMemConsDConvftoi(float* nocapture readonly %ptr) {
1323entry:
1324 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3
1325 %0 = load float, float* %arrayidx, align 4
1326 %conv = fptosi float %0 to i32
1327 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
1328 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2
1329 %1 = load float, float* %arrayidx1, align 4
1330 %conv2 = fptosi float %1 to i32
1331 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
1332 %arrayidx4 = getelementptr inbounds float, float* %ptr, i64 1
1333 %2 = load float, float* %arrayidx4, align 4
1334 %conv5 = fptosi float %2 to i32
1335 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
1336 %3 = load float, float* %ptr, align 4
1337 %conv8 = fptosi float %3 to i32
1338 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
1339 ret <4 x i32> %vecinit9
1340; P9BE-LABEL: fromDiffMemConsDConvftoi
1341; P9LE-LABEL: fromDiffMemConsDConvftoi
1342; P8BE-LABEL: fromDiffMemConsDConvftoi
1343; P8LE-LABEL: fromDiffMemConsDConvftoi
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]1344; P9BE: lxv
1345; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]1346; P9BE: vperm
1347; P9BE: xvcvspsxws
1348; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]1349; P9LE: lxv
1350; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]1351; P9LE: vperm
1352; P9LE: xvcvspsxws
1353; P9LE: blr
1354; P8BE: lxvw4x
1355; P8BE: lxvw4x
1356; P8BE: vperm
1357; P8BE: xvcvspsxws
1358; P8BE: blr
1359; P8LE: lxvd2x
Nemanja Ivanovicb89c27f2017-05-02 01:47:34 +0000[diff] [blame]1360; P8LE-DAG: lvx
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]1361; P8LE: xxswapd
1362; P8LE: vperm
1363; P8LE: xvcvspsxws
1364; P8LE: blr
1365}
1366
1367; Function Attrs: norecurse nounwind readonly
1368define <4 x i32> @fromDiffMemVarAConvftoi(float* nocapture readonly %arr, i32 signext %elem) {
1369entry:
1370 %idxprom = sext i32 %elem to i64
1371 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom
1372 %0 = load float, float* %arrayidx, align 4
1373 %conv = fptosi float %0 to i32
1374 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
1375 %add = add nsw i32 %elem, 1
1376 %idxprom1 = sext i32 %add to i64
1377 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1
1378 %1 = load float, float* %arrayidx2, align 4
1379 %conv3 = fptosi float %1 to i32
1380 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
1381 %add5 = add nsw i32 %elem, 2
1382 %idxprom6 = sext i32 %add5 to i64
1383 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6
1384 %2 = load float, float* %arrayidx7, align 4
1385 %conv8 = fptosi float %2 to i32
1386 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
1387 %add10 = add nsw i32 %elem, 3
1388 %idxprom11 = sext i32 %add10 to i64
1389 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11
1390 %3 = load float, float* %arrayidx12, align 4
1391 %conv13 = fptosi float %3 to i32
1392 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
1393 ret <4 x i32> %vecinit14
1394; P9BE-LABEL: fromDiffMemVarAConvftoi
1395; P9LE-LABEL: fromDiffMemVarAConvftoi
1396; P8BE-LABEL: fromDiffMemVarAConvftoi
1397; P8LE-LABEL: fromDiffMemVarAConvftoi
1398; FIXME: implement finding consecutive loads with pre-inc
1399; P9BE: lfsux
1400; P9LE: lfsux
1401; P8BE: lfsux
1402; P8LE: lfsux
1403}
1404
1405; Function Attrs: norecurse nounwind readonly
1406define <4 x i32> @fromDiffMemVarDConvftoi(float* nocapture readonly %arr, i32 signext %elem) {
1407entry:
1408 %idxprom = sext i32 %elem to i64
1409 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom
1410 %0 = load float, float* %arrayidx, align 4
1411 %conv = fptosi float %0 to i32
1412 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
1413 %sub = add nsw i32 %elem, -1
1414 %idxprom1 = sext i32 %sub to i64
1415 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1
1416 %1 = load float, float* %arrayidx2, align 4
1417 %conv3 = fptosi float %1 to i32
1418 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
1419 %sub5 = add nsw i32 %elem, -2
1420 %idxprom6 = sext i32 %sub5 to i64
1421 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6
1422 %2 = load float, float* %arrayidx7, align 4
1423 %conv8 = fptosi float %2 to i32
1424 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
1425 %sub10 = add nsw i32 %elem, -3
1426 %idxprom11 = sext i32 %sub10 to i64
1427 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11
1428 %3 = load float, float* %arrayidx12, align 4
1429 %conv13 = fptosi float %3 to i32
1430 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
1431 ret <4 x i32> %vecinit14
1432; P9BE-LABEL: fromDiffMemVarDConvftoi
1433; P9LE-LABEL: fromDiffMemVarDConvftoi
1434; P8BE-LABEL: fromDiffMemVarDConvftoi
1435; P8LE-LABEL: fromDiffMemVarDConvftoi
1436; FIXME: implement finding consecutive loads with pre-inc
1437; P9BE: lfsux
1438; P9LE: lfsux
1439; P8BE: lfsux
1440; P8LE: lfsux
1441}
1442
1443; Function Attrs: norecurse nounwind readnone
1444define <4 x i32> @spltRegValConvftoi(float %val) {
1445entry:
1446 %conv = fptosi float %val to i32
1447 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
1448 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
1449 ret <4 x i32> %splat.splat
1450; P9BE-LABEL: spltRegValConvftoi
1451; P9LE-LABEL: spltRegValConvftoi
1452; P8BE-LABEL: spltRegValConvftoi
1453; P8LE-LABEL: spltRegValConvftoi
1454; P9BE: xscvdpsxws f[[REG1:[0-9]+]], f1
1455; P9BE: xxspltw v2, vs[[REG1]], 1
1456; P9BE: blr
1457; P9LE: xscvdpsxws f[[REG1:[0-9]+]], f1
1458; P9LE: xxspltw v2, vs[[REG1]], 1
1459; P9LE: blr
1460; P8BE: xscvdpsxws f[[REG1:[0-9]+]], f1
1461; P8BE: xxspltw v2, vs[[REG1]], 1
1462; P8BE: blr
1463; P8LE: xscvdpsxws f[[REG1:[0-9]+]], f1
1464; P8LE: xxspltw v2, vs[[REG1]], 1
1465; P8LE: blr
1466}
1467
1468; Function Attrs: norecurse nounwind readonly
1469define <4 x i32> @spltMemValConvftoi(float* nocapture readonly %ptr) {
1470entry:
1471 %0 = load float, float* %ptr, align 4
1472 %conv = fptosi float %0 to i32
1473 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
1474 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
1475 ret <4 x i32> %splat.splat
1476; P9BE-LABEL: spltMemValConvftoi
1477; P9LE-LABEL: spltMemValConvftoi
1478; P8BE-LABEL: spltMemValConvftoi
1479; P8LE-LABEL: spltMemValConvftoi
1480; P9BE: lxvwsx [[REG1:[vs0-9]+]], 0, r3
1481; P9BE: xvcvspsxws v2, [[REG1]]
1482; P9LE: [[REG1:[vs0-9]+]], 0, r3
1483; P9LE: xvcvspsxws v2, [[REG1]]
1484; P8BE: lxsspx [[REG1:f[0-9]+]], 0, r3
1485; P8BE: xscvdpsxws f[[REG2:[0-9]+]], [[REG1]]
1486; P8BE: xxspltw v2, vs[[REG2]], 1
1487; P8LE: lxsspx [[REG1:f[0-9]+]], 0, r3
1488; P8LE: xscvdpsxws f[[REG2:[vs0-9]+]], [[REG1]]
1489; P8LE: xxspltw v2, vs[[REG2]], 1
1490}
1491
1492; Function Attrs: norecurse nounwind readnone
1493define <4 x i32> @spltCnstConvdtoi() {
1494entry:
1495 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4>
1496; P9BE-LABEL: spltCnstConvdtoi
1497; P9LE-LABEL: spltCnstConvdtoi
1498; P8BE-LABEL: spltCnstConvdtoi
1499; P8LE-LABEL: spltCnstConvdtoi
1500; P9BE: vspltisw v2, 4
1501; P9BE: blr
1502; P9LE: vspltisw v2, 4
1503; P9LE: blr
1504; P8BE: vspltisw v2, 4
1505; P8BE: blr
1506; P8LE: vspltisw v2, 4
1507; P8LE: blr
1508}
1509
1510; Function Attrs: norecurse nounwind readnone
1511define <4 x i32> @fromRegsConvdtoi(double %a, double %b, double %c, double %d) {
1512entry:
1513 %conv = fptosi double %a to i32
1514 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
1515 %conv1 = fptosi double %b to i32
1516 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1
1517 %conv3 = fptosi double %c to i32
1518 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2
1519 %conv5 = fptosi double %d to i32
1520 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3
1521 ret <4 x i32> %vecinit6
1522; P9BE-LABEL: fromRegsConvdtoi
1523; P9LE-LABEL: fromRegsConvdtoi
1524; P8BE-LABEL: fromRegsConvdtoi
1525; P8LE-LABEL: fromRegsConvdtoi
1526; P9BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3
1527; P9BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4
1528; P9BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
1529; P9BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
1530; P9BE: vmrgew v2, [[REG3]], [[REG4]]
1531; P9BE: xvcvspsxws v2, v2
1532; P9LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1
1533; P9LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2
1534; P9LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
1535; P9LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
1536; P9LE: vmrgew v2, [[REG4]], [[REG3]]
1537; P9LE: xvcvspsxws v2, v2
1538; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3
1539; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4
1540; P8BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
1541; P8BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
1542; P8BE: vmrgew v2, [[REG3]], [[REG4]]
1543; P8BE: xvcvspsxws v2, v2
1544; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1
1545; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2
1546; P8LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
1547; P8LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
1548; P8LE: vmrgew v2, [[REG4]], [[REG3]]
1549; P8LE: xvcvspsxws v2, v2
1550}
1551
1552; Function Attrs: norecurse nounwind readnone
1553define <4 x i32> @fromDiffConstsConvdtoi() {
1554entry:
1555 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422>
1556; P9BE-LABEL: fromDiffConstsConvdtoi
1557; P9LE-LABEL: fromDiffConstsConvdtoi
1558; P8BE-LABEL: fromDiffConstsConvdtoi
1559; P8LE-LABEL: fromDiffConstsConvdtoi
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]1560; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]1561; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]1562; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]1563; P9LE: blr
1564; P8BE: lxvw4x
1565; P8BE: blr
Nemanja Ivanovicb89c27f2017-05-02 01:47:34 +0000[diff] [blame]1566; P8LE: lvx
1567; P8LE-NOT: xxswapd
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]1568; P8LE: blr
1569}
1570
1571; Function Attrs: norecurse nounwind readonly
1572define <4 x i32> @fromDiffMemConsAConvdtoi(double* nocapture readonly %ptr) {
1573entry:
1574 %0 = bitcast double* %ptr to <2 x double>*
1575 %1 = load <2 x double>, <2 x double>* %0, align 8
1576 %2 = fptosi <2 x double> %1 to <2 x i32>
1577 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 2
1578 %3 = bitcast double* %arrayidx4 to <2 x double>*
1579 %4 = load <2 x double>, <2 x double>* %3, align 8
1580 %5 = fptosi <2 x double> %4 to <2 x i32>
1581 %vecinit9 = shufflevector <2 x i32> %2, <2 x i32> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1582 ret <4 x i32> %vecinit9
1583; P9BE-LABEL: fromDiffMemConsAConvdtoi
1584; P9LE-LABEL: fromDiffMemConsAConvdtoi
1585; P8BE-LABEL: fromDiffMemConsAConvdtoi
1586; P8LE-LABEL: fromDiffMemConsAConvdtoi
Nemanja Ivanovic3c7e276d2017-07-13 18:17:10 +0000[diff] [blame^]1587; P9BE-DAG: lxv [[REG1:[vs0-9]+]], 0(r3)
1588; P9BE-DAG: lxv [[REG2:[vs0-9]+]], 16(r3)
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]1589; P9BE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG1]], [[REG2]]
1590; P9BE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG1]], [[REG2]]
1591; P9BE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]]
1592; P9BE-DAG: xvcvdpsp [[REG6:[vs0-9]+]], [[REG4]]
1593; P9BE: vmrgew v2, [[REG6]], [[REG5]]
1594; P9BE: xvcvspsxws v2, v2
Nemanja Ivanovic3c7e276d2017-07-13 18:17:10 +0000[diff] [blame^]1595; P9LE-DAG: lxv [[REG1:[vs0-9]+]], 0(r3)
1596; P9LE-DAG: lxv [[REG2:[vs0-9]+]], 16(r3)
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]1597; P9LE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG2]], [[REG1]]
1598; P9LE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG2]], [[REG1]]
1599; P9LE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]]
1600; P9LE-DAG: xvcvdpsp [[REG6:[vs0-9]+]], [[REG4]]
1601; P9LE: vmrgew v2, [[REG6]], [[REG5]]
1602; P9LE: xvcvspsxws v2, v2
1603; P8BE: lxvd2x [[REG1:[vs0-9]+]], 0, r3
1604; P8BE: lxvd2x [[REG2:[vs0-9]+]], r3, r4
1605; P8BE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG1]], [[REG2]]
1606; P8BE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG1]], [[REG2]]
1607; P8BE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]]
1608; P8BE-DAG: xvcvdpsp [[REG6:[vs0-9]+]], [[REG4]]
1609; P8BE: vmrgew v2, [[REG6]], [[REG5]]
1610; P8BE: xvcvspsxws v2, v2
1611; P8LE: lxvd2x [[REG1:[vs0-9]+]], 0, r3
1612; P8LE: lxvd2x [[REG2:[vs0-9]+]], r3, r4
1613; P8LE-DAG: xxswapd [[REG3:[vs0-9]+]], [[REG1]]
1614; P8LE-DAG: xxswapd [[REG4:[vs0-9]+]], [[REG2]]
1615; P8LE-DAG: xxmrgld [[REG5:[vs0-9]+]], [[REG4]], [[REG3]]
1616; P8LE-DAG: xxmrghd [[REG6:[vs0-9]+]], [[REG4]], [[REG3]]
1617; P8LE-DAG: xvcvdpsp [[REG7:[vs0-9]+]], [[REG5]]
1618; P8LE-DAG: xvcvdpsp [[REG8:[vs0-9]+]], [[REG6]]
1619; P8LE: vmrgew v2, [[REG8]], [[REG7]]
1620; P8LE: xvcvspsxws v2, v2
1621}
1622
1623; Function Attrs: norecurse nounwind readonly
1624define <4 x i32> @fromDiffMemConsDConvdtoi(double* nocapture readonly %ptr) {
1625entry:
1626 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3
1627 %0 = load double, double* %arrayidx, align 8
1628 %conv = fptosi double %0 to i32
1629 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
1630 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2
1631 %1 = load double, double* %arrayidx1, align 8
1632 %conv2 = fptosi double %1 to i32
1633 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
1634 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 1
1635 %2 = load double, double* %arrayidx4, align 8
1636 %conv5 = fptosi double %2 to i32
1637 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
1638 %3 = load double, double* %ptr, align 8
1639 %conv8 = fptosi double %3 to i32
1640 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
1641 ret <4 x i32> %vecinit9
1642; P9BE-LABEL: fromDiffMemConsDConvdtoi
1643; P9LE-LABEL: fromDiffMemConsDConvdtoi
1644; P8BE-LABEL: fromDiffMemConsDConvdtoi
1645; P8LE-LABEL: fromDiffMemConsDConvdtoi
1646; P9BE: lfd
1647; P9BE: lfd
1648; P9BE: lfd
1649; P9BE: lfd
1650; P9BE: xxmrghd
1651; P9BE: xxmrghd
1652; P9BE: xvcvdpsp
1653; P9BE: xvcvdpsp
1654; P9BE: vmrgew
1655; P9BE: xvcvspsxws v2
1656; P9LE: lfd
1657; P9LE: lfd
1658; P9LE: lfd
1659; P9LE: lfd
1660; P9LE: xxmrghd
1661; P9LE: xxmrghd
1662; P9LE: xvcvdpsp
1663; P9LE: xvcvdpsp
1664; P9LE: vmrgew
1665; P9LE: xvcvspsxws v2
1666; P8BE: lxsdx
1667; P8BE: lxsdx
1668; P8BE: lxsdx
1669; P8BE: lxsdx
1670; P8BE: xxmrghd
1671; P8BE: xxmrghd
1672; P8BE: xvcvdpsp
1673; P8BE: xvcvdpsp
1674; P8BE: vmrgew
1675; P8BE: xvcvspsxws v2
1676; P8LE: lxsdx
1677; P8LE: lxsdx
1678; P8LE: lxsdx
1679; P8LE: lxsdx
1680; P8LE: xxmrghd
1681; P8LE: xxmrghd
1682; P8LE: xvcvdpsp
1683; P8LE: xvcvdpsp
1684; P8LE: vmrgew
1685; P8LE: xvcvspsxws v2
1686}
1687
1688; Function Attrs: norecurse nounwind readonly
1689define <4 x i32> @fromDiffMemVarAConvdtoi(double* nocapture readonly %arr, i32 signext %elem) {
1690entry:
1691 %idxprom = sext i32 %elem to i64
1692 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom
1693 %0 = load double, double* %arrayidx, align 8
1694 %conv = fptosi double %0 to i32
1695 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
1696 %add = add nsw i32 %elem, 1
1697 %idxprom1 = sext i32 %add to i64
1698 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1
1699 %1 = load double, double* %arrayidx2, align 8
1700 %conv3 = fptosi double %1 to i32
1701 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
1702 %add5 = add nsw i32 %elem, 2
1703 %idxprom6 = sext i32 %add5 to i64
1704 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6
1705 %2 = load double, double* %arrayidx7, align 8
1706 %conv8 = fptosi double %2 to i32
1707 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
1708 %add10 = add nsw i32 %elem, 3
1709 %idxprom11 = sext i32 %add10 to i64
1710 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11
1711 %3 = load double, double* %arrayidx12, align 8
1712 %conv13 = fptosi double %3 to i32
1713 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
1714 ret <4 x i32> %vecinit14
1715; P9BE-LABEL: fromDiffMemVarAConvdtoi
1716; P9LE-LABEL: fromDiffMemVarAConvdtoi
1717; P8BE-LABEL: fromDiffMemVarAConvdtoi
1718; P8LE-LABEL: fromDiffMemVarAConvdtoi
1719; P9BE: lfdux
1720; P9BE: lfd
1721; P9BE: lfd
1722; P9BE: lfd
1723; P9BE: xxmrghd
1724; P9BE: xxmrghd
1725; P9BE: xvcvdpsp
1726; P9BE: xvcvdpsp
1727; P9BE: vmrgew
1728; P9BE: xvcvspsxws v2
1729; P9LE: lfdux
1730; P9LE: lfd
1731; P9LE: lfd
1732; P9LE: lfd
1733; P9LE: xxmrghd
1734; P9LE: xxmrghd
1735; P9LE: xvcvdpsp
1736; P9LE: xvcvdpsp
1737; P9LE: vmrgew
1738; P9LE: xvcvspsxws v2
1739; P8BE: lfdux
1740; P8BE: lxsdx
1741; P8BE: lxsdx
1742; P8BE: lxsdx
1743; P8BE: xxmrghd
1744; P8BE: xxmrghd
1745; P8BE: xvcvdpsp
1746; P8BE: xvcvdpsp
1747; P8BE: vmrgew
1748; P8BE: xvcvspsxws v2
1749; P8LE: lfdux
1750; P8LE: lxsdx
1751; P8LE: lxsdx
1752; P8LE: lxsdx
1753; P8LE: xxmrghd
1754; P8LE: xxmrghd
1755; P8LE: xvcvdpsp
1756; P8LE: xvcvdpsp
1757; P8LE: vmrgew
1758; P8LE: xvcvspsxws v2
1759}
1760
1761; Function Attrs: norecurse nounwind readonly
1762define <4 x i32> @fromDiffMemVarDConvdtoi(double* nocapture readonly %arr, i32 signext %elem) {
1763entry:
1764 %idxprom = sext i32 %elem to i64
1765 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom
1766 %0 = load double, double* %arrayidx, align 8
1767 %conv = fptosi double %0 to i32
1768 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
1769 %sub = add nsw i32 %elem, -1
1770 %idxprom1 = sext i32 %sub to i64
1771 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1
1772 %1 = load double, double* %arrayidx2, align 8
1773 %conv3 = fptosi double %1 to i32
1774 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
1775 %sub5 = add nsw i32 %elem, -2
1776 %idxprom6 = sext i32 %sub5 to i64
1777 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6
1778 %2 = load double, double* %arrayidx7, align 8
1779 %conv8 = fptosi double %2 to i32
1780 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
1781 %sub10 = add nsw i32 %elem, -3
1782 %idxprom11 = sext i32 %sub10 to i64
1783 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11
1784 %3 = load double, double* %arrayidx12, align 8
1785 %conv13 = fptosi double %3 to i32
1786 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
1787 ret <4 x i32> %vecinit14
1788; P9BE-LABEL: fromDiffMemVarDConvdtoi
1789; P9LE-LABEL: fromDiffMemVarDConvdtoi
1790; P8BE-LABEL: fromDiffMemVarDConvdtoi
1791; P8LE-LABEL: fromDiffMemVarDConvdtoi
1792; P9BE: lfdux
1793; P9BE: lfd
1794; P9BE: lfd
1795; P9BE: lfd
1796; P9BE: xxmrghd
1797; P9BE: xxmrghd
1798; P9BE: xvcvdpsp
1799; P9BE: xvcvdpsp
1800; P9BE: vmrgew
1801; P9BE: xvcvspsxws v2
1802; P9LE: lfdux
1803; P9LE: lfd
1804; P9LE: lfd
1805; P9LE: lfd
1806; P9LE: xxmrghd
1807; P9LE: xxmrghd
1808; P9LE: xvcvdpsp
1809; P9LE: xvcvdpsp
1810; P9LE: vmrgew
1811; P9LE: xvcvspsxws v2
1812; P8BE: lfdux
1813; P8BE: lxsdx
1814; P8BE: lxsdx
1815; P8BE: lxsdx
1816; P8BE: xxmrghd
1817; P8BE: xxmrghd
1818; P8BE: xvcvdpsp
1819; P8BE: xvcvdpsp
1820; P8BE: vmrgew
1821; P8BE: xvcvspsxws v2
1822; P8LE: lfdux
1823; P8LE: lxsdx
1824; P8LE: lxsdx
1825; P8LE: lxsdx
1826; P8LE: xxmrghd
1827; P8LE: xxmrghd
1828; P8LE: xvcvdpsp
1829; P8LE: xvcvdpsp
1830; P8LE: vmrgew
1831; P8LE: xvcvspsxws v2
1832}
1833
1834; Function Attrs: norecurse nounwind readnone
1835define <4 x i32> @spltRegValConvdtoi(double %val) {
1836entry:
1837 %conv = fptosi double %val to i32
1838 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
1839 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
1840 ret <4 x i32> %splat.splat
1841; P9BE-LABEL: spltRegValConvdtoi
1842; P9LE-LABEL: spltRegValConvdtoi
1843; P8BE-LABEL: spltRegValConvdtoi
1844; P8LE-LABEL: spltRegValConvdtoi
1845; P9BE: xscvdpsxws
1846; P9BE: xxspltw
1847; P9BE: blr
1848; P9LE: xscvdpsxws
1849; P9LE: xxspltw
1850; P9LE: blr
1851; P8BE: xscvdpsxws
1852; P8BE: xxspltw
1853; P8BE: blr
1854; P8LE: xscvdpsxws
1855; P8LE: xxspltw
1856; P8LE: blr
1857}
1858
1859; Function Attrs: norecurse nounwind readonly
1860define <4 x i32> @spltMemValConvdtoi(double* nocapture readonly %ptr) {
1861entry:
1862 %0 = load double, double* %ptr, align 8
1863 %conv = fptosi double %0 to i32
1864 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
1865 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
1866 ret <4 x i32> %splat.splat
1867; P9BE-LABEL: spltMemValConvdtoi
1868; P9LE-LABEL: spltMemValConvdtoi
1869; P8BE-LABEL: spltMemValConvdtoi
1870; P8LE-LABEL: spltMemValConvdtoi
1871; P9BE: lfd
1872; P9BE: xscvdpsxws
1873; P9BE: xxspltw
1874; P9BE: blr
1875; P9LE: lfd
1876; P9LE: xscvdpsxws
1877; P9LE: xxspltw
1878; P9LE: blr
1879; P8BE: lxsdx
1880; P8BE: xscvdpsxws
1881; P8BE: xxspltw
1882; P8BE: blr
1883; P8LE: lxsdx
1884; P8LE: xscvdpsxws
1885; P8LE: xxspltw
1886; P8LE: blr
1887}
1888; Function Attrs: norecurse nounwind readnone
1889define <4 x i32> @allZeroui() {
1890entry:
1891 ret <4 x i32> zeroinitializer
1892; P9BE-LABEL: allZeroui
1893; P9LE-LABEL: allZeroui
1894; P8BE-LABEL: allZeroui
1895; P8LE-LABEL: allZeroui
1896; P9BE: xxlxor v2, v2, v2
1897; P9BE: blr
1898; P9LE: xxlxor v2, v2, v2
1899; P9LE: blr
1900; P8BE: xxlxor v2, v2, v2
1901; P8BE: blr
1902; P8LE: xxlxor v2, v2, v2
1903; P8LE: blr
1904}
1905
1906; Function Attrs: norecurse nounwind readnone
1907define <4 x i32> @allOneui() {
1908entry:
1909 ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
1910; P9BE-LABEL: allOneui
1911; P9LE-LABEL: allOneui
1912; P8BE-LABEL: allOneui
1913; P8LE-LABEL: allOneui
1914; P9BE: xxspltib v2, 255
1915; P9BE: blr
1916; P9LE: xxspltib v2, 255
1917; P9LE: blr
1918; P8BE: vspltisb v2, -1
1919; P8BE: blr
1920; P8LE: vspltisb v2, -1
1921; P8LE: blr
1922}
1923
1924; Function Attrs: norecurse nounwind readnone
1925define <4 x i32> @spltConst1ui() {
1926entry:
1927 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1>
1928; P9BE-LABEL: spltConst1ui
1929; P9LE-LABEL: spltConst1ui
1930; P8BE-LABEL: spltConst1ui
1931; P8LE-LABEL: spltConst1ui
1932; P9BE: vspltisw v2, 1
1933; P9BE: blr
1934; P9LE: vspltisw v2, 1
1935; P9LE: blr
1936; P8BE: vspltisw v2, 1
1937; P8BE: blr
1938; P8LE: vspltisw v2, 1
1939; P8LE: blr
1940}
1941
1942; Function Attrs: norecurse nounwind readnone
1943define <4 x i32> @spltConst16kui() {
1944entry:
1945 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>
1946; P9BE-LABEL: spltConst16kui
1947; P9LE-LABEL: spltConst16kui
1948; P8BE-LABEL: spltConst16kui
1949; P8LE-LABEL: spltConst16kui
1950; P9BE: vspltisw v2, -15
1951; P9BE: vsrw v2, v2, v2
1952; P9BE: blr
1953; P9LE: vspltisw v2, -15
1954; P9LE: vsrw v2, v2, v2
1955; P9LE: blr
1956; P8BE: vspltisw v2, -15
1957; P8BE: vsrw v2, v2, v2
1958; P8BE: blr
1959; P8LE: vspltisw v2, -15
1960; P8LE: vsrw v2, v2, v2
1961; P8LE: blr
1962}
1963
1964; Function Attrs: norecurse nounwind readnone
1965define <4 x i32> @spltConst32kui() {
1966entry:
1967 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
1968; P9BE-LABEL: spltConst32kui
1969; P9LE-LABEL: spltConst32kui
1970; P8BE-LABEL: spltConst32kui
1971; P8LE-LABEL: spltConst32kui
1972; P9BE: vspltisw v2, -16
1973; P9BE: vsrw v2, v2, v2
1974; P9BE: blr
1975; P9LE: vspltisw v2, -16
1976; P9LE: vsrw v2, v2, v2
1977; P9LE: blr
1978; P8BE: vspltisw v2, -16
1979; P8BE: vsrw v2, v2, v2
1980; P8BE: blr
1981; P8LE: vspltisw v2, -16
1982; P8LE: vsrw v2, v2, v2
1983; P8LE: blr
1984}
1985
1986; Function Attrs: norecurse nounwind readnone
1987define <4 x i32> @fromRegsui(i32 zeroext %a, i32 zeroext %b, i32 zeroext %c, i32 zeroext %d) {
1988entry:
1989 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0
1990 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1
1991 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2
1992 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3
1993 ret <4 x i32> %vecinit3
1994; P9BE-LABEL: fromRegsui
1995; P9LE-LABEL: fromRegsui
1996; P8BE-LABEL: fromRegsui
1997; P8LE-LABEL: fromRegsui
1998; P9BE-DAG: mtvsrdd [[REG1:v[0-9]+]], r3, r5
1999; P9BE-DAG: mtvsrdd [[REG2:v[0-9]+]], r4, r6
2000; P9BE: vmrgow v2, [[REG1]], [[REG2]]
2001; P9BE: blr
2002; P9LE-DAG: mtvsrdd [[REG1:v[0-9]+]], r5, r3
2003; P9LE-DAG: mtvsrdd [[REG2:v[0-9]+]], r6, r4
2004; P9LE: vmrgow v2, [[REG2]], [[REG1]]
2005; P9LE: blr
2006; P8BE-DAG: mtvsrwz {{[vf]}}[[REG1:[0-9]+]], r3
2007; P8BE-DAG: mtvsrwz {{[vf]}}[[REG2:[0-9]+]], r4
2008; P8BE-DAG: mtvsrwz {{[vf]}}[[REG3:[0-9]+]], r5
2009; P8BE-DAG: mtvsrwz {{[vf]}}[[REG4:[0-9]+]], r6
2010; P8BE-DAG: xxmrghd [[REG5:v[0-9]+]], {{[v][s]*}}[[REG1]], {{[v][s]*}}[[REG3]]
2011; P8BE-DAG: xxmrghd [[REG6:v[0-9]+]], {{[v][s]*}}[[REG2]], {{[v][s]*}}[[REG4]]
2012; P8BE: vmrgow v2, [[REG5]], [[REG6]]
2013; P8LE-DAG: mtvsrwz {{[vf]}}[[REG1:[0-9]+]], r3
2014; P8LE-DAG: mtvsrwz {{[vf]}}[[REG2:[0-9]+]], r4
2015; P8LE-DAG: mtvsrwz {{[vf]}}[[REG3:[0-9]+]], r5
2016; P8LE-DAG: mtvsrwz {{[vf]}}[[REG4:[0-9]+]], r6
2017; P8LE: xxmrghd [[REG5:v[0-9]+]], {{[v][s]*}}[[REG3]], {{[v][s]*}}[[REG1]]
2018; P8LE: xxmrghd [[REG6:v[0-9]+]], {{[v][s]*}}[[REG4]], {{[v][s]*}}[[REG2]]
2019; P8LE: vmrgow v2, [[REG6]], [[REG5]]
2020}
2021
2022; Function Attrs: norecurse nounwind readnone
2023define <4 x i32> @fromDiffConstsui() {
2024entry:
2025 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19>
2026; P9BE-LABEL: fromDiffConstsui
2027; P9LE-LABEL: fromDiffConstsui
2028; P8BE-LABEL: fromDiffConstsui
2029; P8LE-LABEL: fromDiffConstsui
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]2030; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]2031; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]2032; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]2033; P9LE: blr
2034; P8BE: lxvw4x
2035; P8BE: blr
Nemanja Ivanovicb89c27f2017-05-02 01:47:34 +0000[diff] [blame]2036; P8LE: lvx
2037; P8LE-NOT: xxswapd
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]2038; P8LE: blr
2039}
2040
2041; Function Attrs: norecurse nounwind readonly
2042define <4 x i32> @fromDiffMemConsAui(i32* nocapture readonly %arr) {
2043entry:
2044 %0 = load i32, i32* %arr, align 4
2045 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
2046 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 1
2047 %1 = load i32, i32* %arrayidx1, align 4
2048 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
2049 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2
2050 %2 = load i32, i32* %arrayidx3, align 4
2051 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2
2052 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 3
2053 %3 = load i32, i32* %arrayidx5, align 4
2054 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3
2055 ret <4 x i32> %vecinit6
2056; P9BE-LABEL: fromDiffMemConsAui
2057; P9LE-LABEL: fromDiffMemConsAui
2058; P8BE-LABEL: fromDiffMemConsAui
2059; P8LE-LABEL: fromDiffMemConsAui
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]2060; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]2061; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]2062; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]2063; P9LE: blr
2064; P8BE: lxvw4x
2065; P8BE: blr
2066; P8LE: lxvd2x
2067; P8LE: xxswapd
2068; P8LE: blr
2069}
2070
2071; Function Attrs: norecurse nounwind readonly
2072define <4 x i32> @fromDiffMemConsDui(i32* nocapture readonly %arr) {
2073entry:
2074 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 3
2075 %0 = load i32, i32* %arrayidx, align 4
2076 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
2077 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2
2078 %1 = load i32, i32* %arrayidx1, align 4
2079 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
2080 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 1
2081 %2 = load i32, i32* %arrayidx3, align 4
2082 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2
2083 %3 = load i32, i32* %arr, align 4
2084 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3
2085 ret <4 x i32> %vecinit6
2086; P9BE-LABEL: fromDiffMemConsDui
2087; P9LE-LABEL: fromDiffMemConsDui
2088; P8BE-LABEL: fromDiffMemConsDui
2089; P8LE-LABEL: fromDiffMemConsDui
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]2090; P9BE: lxv
2091; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]2092; P9BE: vperm
2093; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]2094; P9LE: lxv
2095; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]2096; P9LE: vperm
2097; P9LE: blr
2098; P8BE: lxvw4x
2099; P8BE: lxvw4x
2100; P8BE: vperm
2101; P8BE: blr
2102; P8LE: lxvd2x
Nemanja Ivanovicb89c27f2017-05-02 01:47:34 +0000[diff] [blame]2103; P8LE-DAG: lvx
2104; P8LE-NOT: xxswapd
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]2105; P8LE: xxswapd
2106; P8LE: vperm
2107; P8LE: blr
2108}
2109
2110; Function Attrs: norecurse nounwind readonly
2111define <4 x i32> @fromDiffMemVarAui(i32* nocapture readonly %arr, i32 signext %elem) {
2112entry:
2113 %idxprom = sext i32 %elem to i64
2114 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom
2115 %0 = load i32, i32* %arrayidx, align 4
2116 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
2117 %add = add nsw i32 %elem, 1
2118 %idxprom1 = sext i32 %add to i64
2119 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1
2120 %1 = load i32, i32* %arrayidx2, align 4
2121 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
2122 %add4 = add nsw i32 %elem, 2
2123 %idxprom5 = sext i32 %add4 to i64
2124 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5
2125 %2 = load i32, i32* %arrayidx6, align 4
2126 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2
2127 %add8 = add nsw i32 %elem, 3
2128 %idxprom9 = sext i32 %add8 to i64
2129 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9
2130 %3 = load i32, i32* %arrayidx10, align 4
2131 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3
2132 ret <4 x i32> %vecinit11
2133; P9BE-LABEL: fromDiffMemVarAui
2134; P9LE-LABEL: fromDiffMemVarAui
2135; P8BE-LABEL: fromDiffMemVarAui
2136; P8LE-LABEL: fromDiffMemVarAui
2137; P9BE: sldi r4, r4, 2
2138; P9BE: lxvx v2, r3, r4
2139; P9BE: blr
2140; P9LE: sldi r4, r4, 2
2141; P9LE: lxvx v2, r3, r4
2142; P9LE: blr
2143; P8BE: sldi r4, r4, 2
2144; P8BE: lxvw4x {{[vs0-9]+}}, r3, r4
2145; P8BE: blr
2146; P8LE: sldi r4, r4, 2
2147; P8LE: lxvd2x {{[vs0-9]+}}, r3, r4
2148; P8LE: xxswapd
2149; P8LE: blr
2150}
2151
2152; Function Attrs: norecurse nounwind readonly
2153define <4 x i32> @fromDiffMemVarDui(i32* nocapture readonly %arr, i32 signext %elem) {
2154entry:
2155 %idxprom = sext i32 %elem to i64
2156 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom
2157 %0 = load i32, i32* %arrayidx, align 4
2158 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
2159 %sub = add nsw i32 %elem, -1
2160 %idxprom1 = sext i32 %sub to i64
2161 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1
2162 %1 = load i32, i32* %arrayidx2, align 4
2163 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
2164 %sub4 = add nsw i32 %elem, -2
2165 %idxprom5 = sext i32 %sub4 to i64
2166 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5
2167 %2 = load i32, i32* %arrayidx6, align 4
2168 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2
2169 %sub8 = add nsw i32 %elem, -3
2170 %idxprom9 = sext i32 %sub8 to i64
2171 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9
2172 %3 = load i32, i32* %arrayidx10, align 4
2173 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3
2174 ret <4 x i32> %vecinit11
2175; P9BE-LABEL: fromDiffMemVarDui
2176; P9LE-LABEL: fromDiffMemVarDui
2177; P8BE-LABEL: fromDiffMemVarDui
2178; P8LE-LABEL: fromDiffMemVarDui
Ehsan Amiri741b3872016-12-16 00:33:07 +0000[diff] [blame]2179; P9BE-DAG: sldi {{r[0-9]+}}, r4, 2
Nemanja Ivanovic3c7e276d2017-07-13 18:17:10 +0000[diff] [blame^]2180; P9BE-DAG: addi r3, r3, -12
2181; P9BE-DAG: lxvx {{v[0-9]+}}, 0, r3
2182; P9BE-DAG: lxvx
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]2183; P9BE: vperm
2184; P9BE: blr
Ehsan Amiri741b3872016-12-16 00:33:07 +0000[diff] [blame]2185; P9LE-DAG: sldi {{r[0-9]+}}, r4, 2
Nemanja Ivanovic3c7e276d2017-07-13 18:17:10 +0000[diff] [blame^]2186; P9LE-DAG: addi r3, r3, -12
2187; P9LE-DAG: lxvx {{v[0-9]+}}, 0, r3
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]2188; P9LE-DAG: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]2189; P9LE: vperm
2190; P9LE: blr
Ehsan Amiri741b3872016-12-16 00:33:07 +0000[diff] [blame]2191; P8BE-DAG: sldi {{r[0-9]+}}, r4, 2
Lei Huang168d14b2017-07-10 16:44:45 +0000[diff] [blame]2192; P8BE-DAG: lxvw4x {{v[0-9]+}}, 0, r3
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]2193; P8BE-DAG: lxvw4x
2194; P8BE: vperm
2195; P8BE: blr
Ehsan Amiri741b3872016-12-16 00:33:07 +0000[diff] [blame]2196; P8LE-DAG: sldi {{r[0-9]+}}, r4, 2
Nemanja Ivanovicb89c27f2017-05-02 01:47:34 +0000[diff] [blame]2197; P8LE-DAG: lvx
2198; P8LE-DAG: lvx
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]2199; P8LE: vperm
2200; P8LE: blr
2201}
2202
2203; Function Attrs: norecurse nounwind readonly
2204define <4 x i32> @fromRandMemConsui(i32* nocapture readonly %arr) {
2205entry:
2206 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 4
2207 %0 = load i32, i32* %arrayidx, align 4
2208 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
2209 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 18
2210 %1 = load i32, i32* %arrayidx1, align 4
2211 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
2212 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2
2213 %2 = load i32, i32* %arrayidx3, align 4
2214 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2
2215 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 88
2216 %3 = load i32, i32* %arrayidx5, align 4
2217 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3
2218 ret <4 x i32> %vecinit6
2219; P9BE-LABEL: fromRandMemConsui
2220; P9LE-LABEL: fromRandMemConsui
2221; P8BE-LABEL: fromRandMemConsui
2222; P8LE-LABEL: fromRandMemConsui
2223; P9BE: lwz
2224; P9BE: lwz
2225; P9BE: lwz
2226; P9BE: lwz
2227; P9BE: mtvsrdd
2228; P9BE: mtvsrdd
2229; P9BE: vmrgow
2230; P9LE: lwz
2231; P9LE: lwz
2232; P9LE: lwz
2233; P9LE: lwz
2234; P9LE: mtvsrdd
2235; P9LE: mtvsrdd
2236; P9LE: vmrgow
2237; P8BE: lwz
2238; P8BE: lwz
2239; P8BE: lwz
2240; P8BE: lwz
2241; P8BE: mtvsrwz
2242; P8BE: mtvsrwz
2243; P8BE: mtvsrwz
2244; P8BE: mtvsrwz
2245; P8BE: xxmrghd
2246; P8BE: xxmrghd
2247; P8BE: vmrgow
2248; P8LE: lwz
2249; P8LE: lwz
2250; P8LE: lwz
2251; P8LE: lwz
2252; P8LE: mtvsrwz
2253; P8LE: mtvsrwz
2254; P8LE: mtvsrwz
2255; P8LE: mtvsrwz
2256; P8LE: xxmrghd
2257; P8LE: xxmrghd
2258; P8LE: vmrgow
2259}
2260
2261; Function Attrs: norecurse nounwind readonly
2262define <4 x i32> @fromRandMemVarui(i32* nocapture readonly %arr, i32 signext %elem) {
2263entry:
2264 %add = add nsw i32 %elem, 4
2265 %idxprom = sext i32 %add to i64
2266 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom
2267 %0 = load i32, i32* %arrayidx, align 4
2268 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
2269 %add1 = add nsw i32 %elem, 1
2270 %idxprom2 = sext i32 %add1 to i64
2271 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 %idxprom2
2272 %1 = load i32, i32* %arrayidx3, align 4
2273 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
2274 %add5 = add nsw i32 %elem, 2
2275 %idxprom6 = sext i32 %add5 to i64
2276 %arrayidx7 = getelementptr inbounds i32, i32* %arr, i64 %idxprom6
2277 %2 = load i32, i32* %arrayidx7, align 4
2278 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2
2279 %add9 = add nsw i32 %elem, 8
2280 %idxprom10 = sext i32 %add9 to i64
2281 %arrayidx11 = getelementptr inbounds i32, i32* %arr, i64 %idxprom10
2282 %3 = load i32, i32* %arrayidx11, align 4
2283 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3
2284 ret <4 x i32> %vecinit12
2285; P9BE-LABEL: fromRandMemVarui
2286; P9LE-LABEL: fromRandMemVarui
2287; P8BE-LABEL: fromRandMemVarui
2288; P8LE-LABEL: fromRandMemVarui
2289; P9BE: sldi r4, r4, 2
2290; P9BE: lwz
2291; P9BE: lwz
2292; P9BE: lwz
2293; P9BE: lwz
2294; P9BE: mtvsrdd
2295; P9BE: mtvsrdd
2296; P9BE: vmrgow
2297; P9LE: sldi r4, r4, 2
2298; P9LE: lwz
2299; P9LE: lwz
2300; P9LE: lwz
2301; P9LE: lwz
2302; P9LE: mtvsrdd
2303; P9LE: mtvsrdd
2304; P9LE: vmrgow
2305; P8BE: sldi r4, r4, 2
2306; P8BE: lwz
2307; P8BE: lwz
2308; P8BE: lwz
2309; P8BE: lwz
2310; P8BE: mtvsrwz
2311; P8BE: mtvsrwz
2312; P8BE: mtvsrwz
2313; P8BE: mtvsrwz
2314; P8BE: xxmrghd
2315; P8BE: xxmrghd
2316; P8BE: vmrgow
2317; P8LE: sldi r4, r4, 2
2318; P8LE: lwz
2319; P8LE: lwz
2320; P8LE: lwz
2321; P8LE: lwz
2322; P8LE: mtvsrwz
2323; P8LE: mtvsrwz
2324; P8LE: mtvsrwz
2325; P8LE: mtvsrwz
2326; P8LE: xxmrghd
2327; P8LE: xxmrghd
2328; P8LE: vmrgow
2329}
2330
2331; Function Attrs: norecurse nounwind readnone
2332define <4 x i32> @spltRegValui(i32 zeroext %val) {
2333entry:
2334 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0
2335 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
2336 ret <4 x i32> %splat.splat
2337; P9BE-LABEL: spltRegValui
2338; P9LE-LABEL: spltRegValui
2339; P8BE-LABEL: spltRegValui
2340; P8LE-LABEL: spltRegValui
2341; P9BE: mtvsrws v2, r3
2342; P9BE: blr
2343; P9LE: mtvsrws v2, r3
2344; P9LE: blr
2345; P8BE: mtvsrwz {{[vsf0-9]+}}, r3
2346; P8BE: xxspltw v2, {{[vsf0-9]+}}, 1
2347; P8BE: blr
2348; P8LE: mtvsrwz {{[vsf0-9]+}}, r3
2349; P8LE: xxspltw v2, {{[vsf0-9]+}}, 1
2350; P8LE: blr
2351}
2352
2353; Function Attrs: norecurse nounwind readonly
2354define <4 x i32> @spltMemValui(i32* nocapture readonly %ptr) {
2355entry:
2356 %0 = load i32, i32* %ptr, align 4
2357 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0
2358 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
2359 ret <4 x i32> %splat.splat
2360; P9BE-LABEL: spltMemValui
2361; P9LE-LABEL: spltMemValui
2362; P8BE-LABEL: spltMemValui
2363; P8LE-LABEL: spltMemValui
2364; P9BE: lxvwsx v2, 0, r3
2365; P9BE: blr
2366; P9LE: lxvwsx v2, 0, r3
2367; P9LE: blr
2368; P8BE: lxsiwax {{[vsf0-9]+}}, 0, r3
2369; P8BE: xxspltw v2, {{[vsf0-9]+}}, 1
2370; P8BE: blr
2371; P8LE: lxsiwax {{[vsf0-9]+}}, 0, r3
2372; P8LE: xxspltw v2, {{[vsf0-9]+}}, 1
2373; P8LE: blr
2374}
2375
2376; Function Attrs: norecurse nounwind readnone
2377define <4 x i32> @spltCnstConvftoui() {
2378entry:
2379 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4>
2380; P9BE-LABEL: spltCnstConvftoui
2381; P9LE-LABEL: spltCnstConvftoui
2382; P8BE-LABEL: spltCnstConvftoui
2383; P8LE-LABEL: spltCnstConvftoui
2384; P9BE: vspltisw v2, 4
2385; P9BE: blr
2386; P9LE: vspltisw v2, 4
2387; P9LE: blr
2388; P8BE: vspltisw v2, 4
2389; P8BE: blr
2390; P8LE: vspltisw v2, 4
2391; P8LE: blr
2392}
2393
2394; Function Attrs: norecurse nounwind readnone
2395define <4 x i32> @fromRegsConvftoui(float %a, float %b, float %c, float %d) {
2396entry:
2397 %conv = fptoui float %a to i32
2398 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
2399 %conv1 = fptoui float %b to i32
2400 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1
2401 %conv3 = fptoui float %c to i32
2402 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2
2403 %conv5 = fptoui float %d to i32
2404 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3
2405 ret <4 x i32> %vecinit6
2406; P9BE-LABEL: fromRegsConvftoui
2407; P9LE-LABEL: fromRegsConvftoui
2408; P8BE-LABEL: fromRegsConvftoui
2409; P8LE-LABEL: fromRegsConvftoui
2410; P9BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3
2411; P9BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4
2412; P9BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
2413; P9BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
2414; P9BE: vmrgew v2, [[REG3]], [[REG4]]
2415; P9BE: xvcvspuxws v2, v2
2416; P9LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1
2417; P9LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2
2418; P9LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
2419; P9LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
2420; P9LE: vmrgew v2, [[REG4]], [[REG3]]
2421; P9LE: xvcvspuxws v2, v2
2422; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3
2423; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4
2424; P8BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
2425; P8BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
2426; P8BE: vmrgew v2, [[REG3]], [[REG4]]
2427; P8BE: xvcvspuxws v2, v2
2428; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1
2429; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2
2430; P8LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
2431; P8LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
2432; P8LE: vmrgew v2, [[REG4]], [[REG3]]
2433; P8LE: xvcvspuxws v2, v2
2434}
2435
2436; Function Attrs: norecurse nounwind readnone
2437define <4 x i32> @fromDiffConstsConvftoui() {
2438entry:
2439 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422>
2440; P9BE-LABEL: fromDiffConstsConvftoui
2441; P9LE-LABEL: fromDiffConstsConvftoui
2442; P8BE-LABEL: fromDiffConstsConvftoui
2443; P8LE-LABEL: fromDiffConstsConvftoui
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]2444; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]2445; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]2446; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]2447; P9LE: blr
2448; P8BE: lxvw4x
2449; P8BE: blr
Nemanja Ivanovicb89c27f2017-05-02 01:47:34 +0000[diff] [blame]2450; P8LE: lvx
2451; P8LE-NOT: xxswapd
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]2452; P8LE: blr
2453}
2454
2455; Function Attrs: norecurse nounwind readonly
2456define <4 x i32> @fromDiffMemConsAConvftoui(float* nocapture readonly %ptr) {
2457entry:
2458 %0 = bitcast float* %ptr to <4 x float>*
2459 %1 = load <4 x float>, <4 x float>* %0, align 4
2460 %2 = fptoui <4 x float> %1 to <4 x i32>
2461 ret <4 x i32> %2
2462; P9BE-LABEL: fromDiffMemConsAConvftoui
2463; P9LE-LABEL: fromDiffMemConsAConvftoui
2464; P8BE-LABEL: fromDiffMemConsAConvftoui
2465; P8LE-LABEL: fromDiffMemConsAConvftoui
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]2466; P9BE: lxv [[REG1:[vs0-9]+]], 0(r3)
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]2467; P9BE: xvcvspuxws v2, [[REG1]]
2468; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]2469; P9LE: lxv [[REG1:[vs0-9]+]], 0(r3)
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]2470; P9LE: xvcvspuxws v2, [[REG1]]
2471; P9LE: blr
2472; P8BE: lxvw4x [[REG1:[vs0-9]+]], 0, r3
2473; P8BE: xvcvspuxws v2, [[REG1]]
2474; P8BE: blr
2475; P8LE: lxvd2x [[REG1:[vs0-9]+]], 0, r3
2476; P8LE: xxswapd v2, [[REG1]]
2477; P8LE: xvcvspuxws v2, v2
2478; P8LE: blr
2479}
2480
2481; Function Attrs: norecurse nounwind readonly
2482define <4 x i32> @fromDiffMemConsDConvftoui(float* nocapture readonly %ptr) {
2483entry:
2484 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3
2485 %0 = load float, float* %arrayidx, align 4
2486 %conv = fptoui float %0 to i32
2487 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
2488 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2
2489 %1 = load float, float* %arrayidx1, align 4
2490 %conv2 = fptoui float %1 to i32
2491 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
2492 %arrayidx4 = getelementptr inbounds float, float* %ptr, i64 1
2493 %2 = load float, float* %arrayidx4, align 4
2494 %conv5 = fptoui float %2 to i32
2495 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
2496 %3 = load float, float* %ptr, align 4
2497 %conv8 = fptoui float %3 to i32
2498 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
2499 ret <4 x i32> %vecinit9
2500; P9BE-LABEL: fromDiffMemConsDConvftoui
2501; P9LE-LABEL: fromDiffMemConsDConvftoui
2502; P8BE-LABEL: fromDiffMemConsDConvftoui
2503; P8LE-LABEL: fromDiffMemConsDConvftoui
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]2504; P9BE: lxv
2505; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]2506; P9BE: vperm
2507; P9BE: xvcvspuxws
2508; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]2509; P9LE: lxv
2510; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]2511; P9LE: vperm
2512; P9LE: xvcvspuxws
2513; P9LE: blr
2514; P8BE: lxvw4x
2515; P8BE: lxvw4x
2516; P8BE: vperm
2517; P8BE: xvcvspuxws
2518; P8BE: blr
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]2519; P8LE-DAG: lxvd2x
Nemanja Ivanovicb89c27f2017-05-02 01:47:34 +0000[diff] [blame]2520; P8LE-DAG: lvx
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]2521; P8LE: xxswapd
2522; P8LE: vperm
2523; P8LE: xvcvspuxws
2524; P8LE: blr
2525}
2526
2527; Function Attrs: norecurse nounwind readonly
2528define <4 x i32> @fromDiffMemVarAConvftoui(float* nocapture readonly %arr, i32 signext %elem) {
2529entry:
2530 %idxprom = sext i32 %elem to i64
2531 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom
2532 %0 = load float, float* %arrayidx, align 4
2533 %conv = fptoui float %0 to i32
2534 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
2535 %add = add nsw i32 %elem, 1
2536 %idxprom1 = sext i32 %add to i64
2537 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1
2538 %1 = load float, float* %arrayidx2, align 4
2539 %conv3 = fptoui float %1 to i32
2540 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
2541 %add5 = add nsw i32 %elem, 2
2542 %idxprom6 = sext i32 %add5 to i64
2543 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6
2544 %2 = load float, float* %arrayidx7, align 4
2545 %conv8 = fptoui float %2 to i32
2546 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
2547 %add10 = add nsw i32 %elem, 3
2548 %idxprom11 = sext i32 %add10 to i64
2549 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11
2550 %3 = load float, float* %arrayidx12, align 4
2551 %conv13 = fptoui float %3 to i32
2552 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
2553 ret <4 x i32> %vecinit14
2554; P9BE-LABEL: fromDiffMemVarAConvftoui
2555; P9LE-LABEL: fromDiffMemVarAConvftoui
2556; P8BE-LABEL: fromDiffMemVarAConvftoui
2557; P8LE-LABEL: fromDiffMemVarAConvftoui
2558; FIXME: implement finding consecutive loads with pre-inc
2559; P9BE: lfsux
2560; P9LE: lfsux
2561; P8BE: lfsux
2562; P8LE: lfsux
2563}
2564
2565; Function Attrs: norecurse nounwind readonly
2566define <4 x i32> @fromDiffMemVarDConvftoui(float* nocapture readonly %arr, i32 signext %elem) {
2567entry:
2568 %idxprom = sext i32 %elem to i64
2569 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom
2570 %0 = load float, float* %arrayidx, align 4
2571 %conv = fptoui float %0 to i32
2572 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
2573 %sub = add nsw i32 %elem, -1
2574 %idxprom1 = sext i32 %sub to i64
2575 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1
2576 %1 = load float, float* %arrayidx2, align 4
2577 %conv3 = fptoui float %1 to i32
2578 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
2579 %sub5 = add nsw i32 %elem, -2
2580 %idxprom6 = sext i32 %sub5 to i64
2581 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6
2582 %2 = load float, float* %arrayidx7, align 4
2583 %conv8 = fptoui float %2 to i32
2584 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
2585 %sub10 = add nsw i32 %elem, -3
2586 %idxprom11 = sext i32 %sub10 to i64
2587 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11
2588 %3 = load float, float* %arrayidx12, align 4
2589 %conv13 = fptoui float %3 to i32
2590 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
2591 ret <4 x i32> %vecinit14
2592; P9BE-LABEL: fromDiffMemVarDConvftoui
2593; P9LE-LABEL: fromDiffMemVarDConvftoui
2594; P8BE-LABEL: fromDiffMemVarDConvftoui
2595; P8LE-LABEL: fromDiffMemVarDConvftoui
2596; FIXME: implement finding consecutive loads with pre-inc
2597; P9BE: lfsux
2598; P9LE: lfsux
2599; P8BE: lfsux
2600; P8LE: lfsux
2601}
2602
2603; Function Attrs: norecurse nounwind readnone
2604define <4 x i32> @spltRegValConvftoui(float %val) {
2605entry:
2606 %conv = fptoui float %val to i32
2607 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
2608 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
2609 ret <4 x i32> %splat.splat
2610; P9BE-LABEL: spltRegValConvftoui
2611; P9LE-LABEL: spltRegValConvftoui
2612; P8BE-LABEL: spltRegValConvftoui
2613; P8LE-LABEL: spltRegValConvftoui
2614; P9BE: xscvdpuxws f[[REG1:[0-9]+]], f1
2615; P9BE: xxspltw v2, vs[[REG1]], 1
2616; P9BE: blr
2617; P9LE: xscvdpuxws f[[REG1:[0-9]+]], f1
2618; P9LE: xxspltw v2, vs[[REG1]], 1
2619; P9LE: blr
2620; P8BE: xscvdpuxws f[[REG1:[0-9]+]], f1
2621; P8BE: xxspltw v2, vs[[REG1]], 1
2622; P8BE: blr
2623; P8LE: xscvdpuxws f[[REG1:[0-9]+]], f1
2624; P8LE: xxspltw v2, vs[[REG1]], 1
2625; P8LE: blr
2626}
2627
2628; Function Attrs: norecurse nounwind readonly
2629define <4 x i32> @spltMemValConvftoui(float* nocapture readonly %ptr) {
2630entry:
2631 %0 = load float, float* %ptr, align 4
2632 %conv = fptoui float %0 to i32
2633 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
2634 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
2635 ret <4 x i32> %splat.splat
2636; P9BE-LABEL: spltMemValConvftoui
2637; P9LE-LABEL: spltMemValConvftoui
2638; P8BE-LABEL: spltMemValConvftoui
2639; P8LE-LABEL: spltMemValConvftoui
2640; P9BE: lxvwsx [[REG1:[vs0-9]+]], 0, r3
2641; P9BE: xvcvspuxws v2, [[REG1]]
2642; P9LE: [[REG1:[vs0-9]+]], 0, r3
2643; P9LE: xvcvspuxws v2, [[REG1]]
2644; P8BE: lxsspx [[REG1:f[0-9]+]], 0, r3
2645; P8BE: xscvdpuxws f[[REG2:[0-9]+]], [[REG1]]
2646; P8BE: xxspltw v2, vs[[REG2]], 1
2647; P8LE: lxsspx [[REG1:f[0-9]+]], 0, r3
2648; P8LE: xscvdpuxws f[[REG2:[vs0-9]+]], [[REG1]]
2649; P8LE: xxspltw v2, vs[[REG2]], 1
2650}
2651
2652; Function Attrs: norecurse nounwind readnone
2653define <4 x i32> @spltCnstConvdtoui() {
2654entry:
2655 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4>
2656; P9BE-LABEL: spltCnstConvdtoui
2657; P9LE-LABEL: spltCnstConvdtoui
2658; P8BE-LABEL: spltCnstConvdtoui
2659; P8LE-LABEL: spltCnstConvdtoui
2660; P9BE: vspltisw v2, 4
2661; P9BE: blr
2662; P9LE: vspltisw v2, 4
2663; P9LE: blr
2664; P8BE: vspltisw v2, 4
2665; P8BE: blr
2666; P8LE: vspltisw v2, 4
2667; P8LE: blr
2668}
2669
2670; Function Attrs: norecurse nounwind readnone
2671define <4 x i32> @fromRegsConvdtoui(double %a, double %b, double %c, double %d) {
2672entry:
2673 %conv = fptoui double %a to i32
2674 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
2675 %conv1 = fptoui double %b to i32
2676 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1
2677 %conv3 = fptoui double %c to i32
2678 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2
2679 %conv5 = fptoui double %d to i32
2680 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3
2681 ret <4 x i32> %vecinit6
2682; P9BE-LABEL: fromRegsConvdtoui
2683; P9LE-LABEL: fromRegsConvdtoui
2684; P8BE-LABEL: fromRegsConvdtoui
2685; P8LE-LABEL: fromRegsConvdtoui
2686; P9BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3
2687; P9BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4
2688; P9BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
2689; P9BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
2690; P9BE: vmrgew v2, [[REG3]], [[REG4]]
2691; P9BE: xvcvspuxws v2, v2
2692; P9LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1
2693; P9LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2
2694; P9LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
2695; P9LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
2696; P9LE: vmrgew v2, [[REG4]], [[REG3]]
2697; P9LE: xvcvspuxws v2, v2
2698; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3
2699; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4
2700; P8BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
2701; P8BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
2702; P8BE: vmrgew v2, [[REG3]], [[REG4]]
2703; P8BE: xvcvspuxws v2, v2
2704; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1
2705; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2
2706; P8LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]]
2707; P8LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]]
2708; P8LE: vmrgew v2, [[REG4]], [[REG3]]
2709; P8LE: xvcvspuxws v2, v2
2710}
2711
2712; Function Attrs: norecurse nounwind readnone
2713define <4 x i32> @fromDiffConstsConvdtoui() {
2714entry:
2715 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422>
2716; P9BE-LABEL: fromDiffConstsConvdtoui
2717; P9LE-LABEL: fromDiffConstsConvdtoui
2718; P8BE-LABEL: fromDiffConstsConvdtoui
2719; P8LE-LABEL: fromDiffConstsConvdtoui
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]2720; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]2721; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]2722; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]2723; P9LE: blr
2724; P8BE: lxvw4x
2725; P8BE: blr
Nemanja Ivanovicb89c27f2017-05-02 01:47:34 +0000[diff] [blame]2726; P8LE: lvx
2727; P8LE-NOT: xxswapd
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]2728; P8LE: blr
2729}
2730
2731; Function Attrs: norecurse nounwind readonly
2732define <4 x i32> @fromDiffMemConsAConvdtoui(double* nocapture readonly %ptr) {
2733entry:
2734 %0 = bitcast double* %ptr to <2 x double>*
2735 %1 = load <2 x double>, <2 x double>* %0, align 8
2736 %2 = fptoui <2 x double> %1 to <2 x i32>
2737 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 2
2738 %3 = bitcast double* %arrayidx4 to <2 x double>*
2739 %4 = load <2 x double>, <2 x double>* %3, align 8
2740 %5 = fptoui <2 x double> %4 to <2 x i32>
2741 %vecinit9 = shufflevector <2 x i32> %2, <2 x i32> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
2742 ret <4 x i32> %vecinit9
2743; P9BE-LABEL: fromDiffMemConsAConvdtoui
2744; P9LE-LABEL: fromDiffMemConsAConvdtoui
2745; P8BE-LABEL: fromDiffMemConsAConvdtoui
2746; P8LE-LABEL: fromDiffMemConsAConvdtoui
Nemanja Ivanovic3c7e276d2017-07-13 18:17:10 +0000[diff] [blame^]2747; P9BE-DAG: lxv [[REG1:[vs0-9]+]], 0(r3)
2748; P9BE-DAG: lxv [[REG2:[vs0-9]+]], 16(r3)
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]2749; P9BE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG1]], [[REG2]]
2750; P9BE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG1]], [[REG2]]
2751; P9BE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]]
2752; P9BE-DAG: xvcvdpsp [[REG6:[vs0-9]+]], [[REG4]]
2753; P9BE: vmrgew v2, [[REG6]], [[REG5]]
2754; P9BE: xvcvspuxws v2, v2
Nemanja Ivanovic3c7e276d2017-07-13 18:17:10 +0000[diff] [blame^]2755; P9LE-DAG: lxv [[REG1:[vs0-9]+]], 0(r3)
2756; P9LE-DAG: lxv [[REG2:[vs0-9]+]], 16(r3)
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]2757; P9LE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG2]], [[REG1]]
2758; P9LE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG2]], [[REG1]]
2759; P9LE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]]
2760; P9LE-DAG: xvcvdpsp [[REG6:[vs0-9]+]], [[REG4]]
2761; P9LE: vmrgew v2, [[REG6]], [[REG5]]
2762; P9LE: xvcvspuxws v2, v2
2763; P8BE: lxvd2x [[REG1:[vs0-9]+]], 0, r3
2764; P8BE: lxvd2x [[REG2:[vs0-9]+]], r3, r4
2765; P8BE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG1]], [[REG2]]
2766; P8BE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG1]], [[REG2]]
2767; P8BE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]]
2768; P8BE-DAG: xvcvdpsp [[REG6:[vs0-9]+]], [[REG4]]
2769; P8BE: vmrgew v2, [[REG6]], [[REG5]]
2770; P8BE: xvcvspuxws v2, v2
2771; P8LE: lxvd2x [[REG1:[vs0-9]+]], 0, r3
2772; P8LE: lxvd2x [[REG2:[vs0-9]+]], r3, r4
2773; P8LE-DAG: xxswapd [[REG3:[vs0-9]+]], [[REG1]]
2774; P8LE-DAG: xxswapd [[REG4:[vs0-9]+]], [[REG2]]
2775; P8LE-DAG: xxmrgld [[REG5:[vs0-9]+]], [[REG4]], [[REG3]]
2776; P8LE-DAG: xxmrghd [[REG6:[vs0-9]+]], [[REG4]], [[REG3]]
2777; P8LE-DAG: xvcvdpsp [[REG7:[vs0-9]+]], [[REG5]]
2778; P8LE-DAG: xvcvdpsp [[REG8:[vs0-9]+]], [[REG6]]
2779; P8LE: vmrgew v2, [[REG8]], [[REG7]]
2780; P8LE: xvcvspuxws v2, v2
2781}
2782
2783; Function Attrs: norecurse nounwind readonly
2784define <4 x i32> @fromDiffMemConsDConvdtoui(double* nocapture readonly %ptr) {
2785entry:
2786 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3
2787 %0 = load double, double* %arrayidx, align 8
2788 %conv = fptoui double %0 to i32
2789 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
2790 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2
2791 %1 = load double, double* %arrayidx1, align 8
2792 %conv2 = fptoui double %1 to i32
2793 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
2794 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 1
2795 %2 = load double, double* %arrayidx4, align 8
2796 %conv5 = fptoui double %2 to i32
2797 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
2798 %3 = load double, double* %ptr, align 8
2799 %conv8 = fptoui double %3 to i32
2800 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
2801 ret <4 x i32> %vecinit9
2802; P9BE-LABEL: fromDiffMemConsDConvdtoui
2803; P9LE-LABEL: fromDiffMemConsDConvdtoui
2804; P8BE-LABEL: fromDiffMemConsDConvdtoui
2805; P8LE-LABEL: fromDiffMemConsDConvdtoui
2806; P9BE: lfd
2807; P9BE: lfd
2808; P9BE: lfd
2809; P9BE: lfd
2810; P9BE: xxmrghd
2811; P9BE: xxmrghd
2812; P9BE: xvcvdpsp
2813; P9BE: xvcvdpsp
2814; P9BE: vmrgew
2815; P9BE: xvcvspuxws v2
2816; P9LE: lfd
2817; P9LE: lfd
2818; P9LE: lfd
2819; P9LE: lfd
2820; P9LE: xxmrghd
2821; P9LE: xxmrghd
2822; P9LE: xvcvdpsp
2823; P9LE: xvcvdpsp
2824; P9LE: vmrgew
2825; P9LE: xvcvspuxws v2
2826; P8BE: lxsdx
2827; P8BE: lxsdx
2828; P8BE: lxsdx
2829; P8BE: lxsdx
2830; P8BE: xxmrghd
2831; P8BE: xxmrghd
2832; P8BE: xvcvdpsp
2833; P8BE: xvcvdpsp
2834; P8BE: vmrgew
2835; P8BE: xvcvspuxws v2
2836; P8LE: lxsdx
2837; P8LE: lxsdx
2838; P8LE: lxsdx
2839; P8LE: lxsdx
2840; P8LE: xxmrghd
2841; P8LE: xxmrghd
2842; P8LE: xvcvdpsp
2843; P8LE: xvcvdpsp
2844; P8LE: vmrgew
2845; P8LE: xvcvspuxws v2
2846}
2847
2848; Function Attrs: norecurse nounwind readonly
2849define <4 x i32> @fromDiffMemVarAConvdtoui(double* nocapture readonly %arr, i32 signext %elem) {
2850entry:
2851 %idxprom = sext i32 %elem to i64
2852 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom
2853 %0 = load double, double* %arrayidx, align 8
2854 %conv = fptoui double %0 to i32
2855 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
2856 %add = add nsw i32 %elem, 1
2857 %idxprom1 = sext i32 %add to i64
2858 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1
2859 %1 = load double, double* %arrayidx2, align 8
2860 %conv3 = fptoui double %1 to i32
2861 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
2862 %add5 = add nsw i32 %elem, 2
2863 %idxprom6 = sext i32 %add5 to i64
2864 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6
2865 %2 = load double, double* %arrayidx7, align 8
2866 %conv8 = fptoui double %2 to i32
2867 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
2868 %add10 = add nsw i32 %elem, 3
2869 %idxprom11 = sext i32 %add10 to i64
2870 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11
2871 %3 = load double, double* %arrayidx12, align 8
2872 %conv13 = fptoui double %3 to i32
2873 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
2874 ret <4 x i32> %vecinit14
2875; P9BE-LABEL: fromDiffMemVarAConvdtoui
2876; P9LE-LABEL: fromDiffMemVarAConvdtoui
2877; P8BE-LABEL: fromDiffMemVarAConvdtoui
2878; P8LE-LABEL: fromDiffMemVarAConvdtoui
2879; P9BE: lfdux
2880; P9BE: lfd
2881; P9BE: lfd
2882; P9BE: lfd
2883; P9BE: xxmrghd
2884; P9BE: xxmrghd
2885; P9BE: xvcvdpsp
2886; P9BE: xvcvdpsp
2887; P9BE: vmrgew
2888; P9BE: xvcvspuxws v2
2889; P9LE: lfdux
2890; P9LE: lfd
2891; P9LE: lfd
2892; P9LE: lfd
2893; P9LE: xxmrghd
2894; P9LE: xxmrghd
2895; P9LE: xvcvdpsp
2896; P9LE: xvcvdpsp
2897; P9LE: vmrgew
2898; P9LE: xvcvspuxws v2
2899; P8BE: lfdux
2900; P8BE: lxsdx
2901; P8BE: lxsdx
2902; P8BE: lxsdx
2903; P8BE: xxmrghd
2904; P8BE: xxmrghd
2905; P8BE: xvcvdpsp
2906; P8BE: xvcvdpsp
2907; P8BE: vmrgew
2908; P8BE: xvcvspuxws v2
2909; P8LE: lfdux
2910; P8LE: lxsdx
2911; P8LE: lxsdx
2912; P8LE: lxsdx
2913; P8LE: xxmrghd
2914; P8LE: xxmrghd
2915; P8LE: xvcvdpsp
2916; P8LE: xvcvdpsp
2917; P8LE: vmrgew
2918; P8LE: xvcvspuxws v2
2919}
2920
2921; Function Attrs: norecurse nounwind readonly
2922define <4 x i32> @fromDiffMemVarDConvdtoui(double* nocapture readonly %arr, i32 signext %elem) {
2923entry:
2924 %idxprom = sext i32 %elem to i64
2925 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom
2926 %0 = load double, double* %arrayidx, align 8
2927 %conv = fptoui double %0 to i32
2928 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
2929 %sub = add nsw i32 %elem, -1
2930 %idxprom1 = sext i32 %sub to i64
2931 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1
2932 %1 = load double, double* %arrayidx2, align 8
2933 %conv3 = fptoui double %1 to i32
2934 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
2935 %sub5 = add nsw i32 %elem, -2
2936 %idxprom6 = sext i32 %sub5 to i64
2937 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6
2938 %2 = load double, double* %arrayidx7, align 8
2939 %conv8 = fptoui double %2 to i32
2940 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
2941 %sub10 = add nsw i32 %elem, -3
2942 %idxprom11 = sext i32 %sub10 to i64
2943 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11
2944 %3 = load double, double* %arrayidx12, align 8
2945 %conv13 = fptoui double %3 to i32
2946 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
2947 ret <4 x i32> %vecinit14
2948; P9BE-LABEL: fromDiffMemVarDConvdtoui
2949; P9LE-LABEL: fromDiffMemVarDConvdtoui
2950; P8BE-LABEL: fromDiffMemVarDConvdtoui
2951; P8LE-LABEL: fromDiffMemVarDConvdtoui
2952; P9BE: lfdux
2953; P9BE: lfd
2954; P9BE: lfd
2955; P9BE: lfd
2956; P9BE: xxmrghd
2957; P9BE: xxmrghd
2958; P9BE: xvcvdpsp
2959; P9BE: xvcvdpsp
2960; P9BE: vmrgew
2961; P9BE: xvcvspuxws v2
2962; P9LE: lfdux
2963; P9LE: lfd
2964; P9LE: lfd
2965; P9LE: lfd
2966; P9LE: xxmrghd
2967; P9LE: xxmrghd
2968; P9LE: xvcvdpsp
2969; P9LE: xvcvdpsp
2970; P9LE: vmrgew
2971; P9LE: xvcvspuxws v2
2972; P8BE: lfdux
2973; P8BE: lxsdx
2974; P8BE: lxsdx
2975; P8BE: lxsdx
2976; P8BE: xxmrghd
2977; P8BE: xxmrghd
2978; P8BE: xvcvdpsp
2979; P8BE: xvcvdpsp
2980; P8BE: vmrgew
2981; P8BE: xvcvspuxws v2
2982; P8LE: lfdux
2983; P8LE: lxsdx
2984; P8LE: lxsdx
2985; P8LE: lxsdx
2986; P8LE: xxmrghd
2987; P8LE: xxmrghd
2988; P8LE: xvcvdpsp
2989; P8LE: xvcvdpsp
2990; P8LE: vmrgew
2991; P8LE: xvcvspuxws v2
2992}
2993
2994; Function Attrs: norecurse nounwind readnone
2995define <4 x i32> @spltRegValConvdtoui(double %val) {
2996entry:
2997 %conv = fptoui double %val to i32
2998 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
2999 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
3000 ret <4 x i32> %splat.splat
3001; P9BE-LABEL: spltRegValConvdtoui
3002; P9LE-LABEL: spltRegValConvdtoui
3003; P8BE-LABEL: spltRegValConvdtoui
3004; P8LE-LABEL: spltRegValConvdtoui
3005; P9BE: xscvdpuxws
3006; P9BE: xxspltw
3007; P9BE: blr
3008; P9LE: xscvdpuxws
3009; P9LE: xxspltw
3010; P9LE: blr
3011; P8BE: xscvdpuxws
3012; P8BE: xxspltw
3013; P8BE: blr
3014; P8LE: xscvdpuxws
3015; P8LE: xxspltw
3016; P8LE: blr
3017}
3018
3019; Function Attrs: norecurse nounwind readonly
3020define <4 x i32> @spltMemValConvdtoui(double* nocapture readonly %ptr) {
3021entry:
3022 %0 = load double, double* %ptr, align 8
3023 %conv = fptoui double %0 to i32
3024 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
3025 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
3026 ret <4 x i32> %splat.splat
3027; P9BE-LABEL: spltMemValConvdtoui
3028; P9LE-LABEL: spltMemValConvdtoui
3029; P8BE-LABEL: spltMemValConvdtoui
3030; P8LE-LABEL: spltMemValConvdtoui
3031; P9BE: lfd
3032; P9BE: xscvdpuxws
3033; P9BE: xxspltw
3034; P9BE: blr
3035; P9LE: lfd
3036; P9LE: xscvdpuxws
3037; P9LE: xxspltw
3038; P9LE: blr
3039; P8BE: lxsdx
3040; P8BE: xscvdpuxws
3041; P8BE: xxspltw
3042; P8BE: blr
3043; P8LE: lxsdx
3044; P8LE: xscvdpuxws
3045; P8LE: xxspltw
3046; P8LE: blr
3047}
3048; Function Attrs: norecurse nounwind readnone
3049define <2 x i64> @allZeroll() {
3050entry:
3051 ret <2 x i64> zeroinitializer
3052; P9BE-LABEL: allZeroll
3053; P9LE-LABEL: allZeroll
3054; P8BE-LABEL: allZeroll
3055; P8LE-LABEL: allZeroll
3056; P9BE: xxlxor v2, v2, v2
3057; P9BE: blr
3058; P9LE: xxlxor v2, v2, v2
3059; P9LE: blr
3060; P8BE: xxlxor v2, v2, v2
3061; P8BE: blr
3062; P8LE: xxlxor v2, v2, v2
3063; P8LE: blr
3064}
3065
3066; Function Attrs: norecurse nounwind readnone
3067define <2 x i64> @allOnell() {
3068entry:
3069 ret <2 x i64> <i64 -1, i64 -1>
3070; P9BE-LABEL: allOnell
3071; P9LE-LABEL: allOnell
3072; P8BE-LABEL: allOnell
3073; P8LE-LABEL: allOnell
3074; P9BE: xxspltib v2, 255
3075; P9BE: blr
3076; P9LE: xxspltib v2, 255
3077; P9LE: blr
3078; P8BE: vspltisb v2, -1
3079; P8BE: blr
3080; P8LE: vspltisb v2, -1
3081; P8LE: blr
3082}
3083
3084; Function Attrs: norecurse nounwind readnone
3085define <2 x i64> @spltConst1ll() {
3086entry:
3087 ret <2 x i64> <i64 1, i64 1>
3088; P9BE-LABEL: spltConst1ll
3089; P9LE-LABEL: spltConst1ll
3090; P8BE-LABEL: spltConst1ll
3091; P8LE-LABEL: spltConst1ll
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]3092; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]3093; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]3094; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]3095; P9LE: blr
3096; P8BE: lxvd2x
3097; P8BE: blr
3098; P8LE: lxvd2x
3099; P8LE: blr
3100}
3101
3102; Function Attrs: norecurse nounwind readnone
3103define <2 x i64> @spltConst16kll() {
3104entry:
3105 ret <2 x i64> <i64 32767, i64 32767>
3106; P9BE-LABEL: spltConst16kll
3107; P9LE-LABEL: spltConst16kll
3108; P8BE-LABEL: spltConst16kll
3109; P8LE-LABEL: spltConst16kll
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]3110; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]3111; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]3112; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]3113; P9LE: blr
3114; P8BE: lxvd2x
3115; P8BE: blr
3116; P8LE: lxvd2x
3117; P8LE: blr
3118}
3119
3120; Function Attrs: norecurse nounwind readnone
3121define <2 x i64> @spltConst32kll() {
3122entry:
3123 ret <2 x i64> <i64 65535, i64 65535>
3124; P9BE-LABEL: spltConst32kll
3125; P9LE-LABEL: spltConst32kll
3126; P8BE-LABEL: spltConst32kll
3127; P8LE-LABEL: spltConst32kll
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]3128; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]3129; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]3130; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]3131; P9LE: blr
3132; P8BE: lxvd2x
3133; P8BE: blr
3134; P8LE: lxvd2x
3135; P8LE: blr
3136}
3137
3138; Function Attrs: norecurse nounwind readnone
3139define <2 x i64> @fromRegsll(i64 %a, i64 %b) {
3140entry:
3141 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0
3142 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1
3143 ret <2 x i64> %vecinit1
3144; P9BE-LABEL: fromRegsll
3145; P9LE-LABEL: fromRegsll
3146; P8BE-LABEL: fromRegsll
3147; P8LE-LABEL: fromRegsll
3148; P9BE: mtvsrdd v2, r3, r4
3149; P9BE: blr
3150; P9LE: mtvsrdd v2, r4, r3
3151; P9LE: blr
3152; P8BE-DAG: mtvsrd {{[vsf0-9]+}}, r3
3153; P8BE-DAG: mtvsrd {{[vsf0-9]+}}, r4
3154; P8BE: xxmrghd v2
3155; P8BE: blr
3156; P8LE-DAG: mtvsrd {{[vsf0-9]+}}, r3
3157; P8LE-DAG: mtvsrd {{[vsf0-9]+}}, r4
3158; P8LE: xxmrghd v2
3159; P8LE: blr
3160}
3161
3162; Function Attrs: norecurse nounwind readnone
3163define <2 x i64> @fromDiffConstsll() {
3164entry:
3165 ret <2 x i64> <i64 242, i64 -113>
3166; P9BE-LABEL: fromDiffConstsll
3167; P9LE-LABEL: fromDiffConstsll
3168; P8BE-LABEL: fromDiffConstsll
3169; P8LE-LABEL: fromDiffConstsll
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]3170; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]3171; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]3172; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]3173; P9LE: blr
3174; P8BE: lxvd2x
3175; P8BE: blr
3176; P8LE: lxvd2x
3177; P8LE: blr
3178}
3179
3180; Function Attrs: norecurse nounwind readonly
3181define <2 x i64> @fromDiffMemConsAll(i64* nocapture readonly %arr) {
3182entry:
3183 %0 = load i64, i64* %arr, align 8
3184 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
3185 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 1
3186 %1 = load i64, i64* %arrayidx1, align 8
3187 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
3188 ret <2 x i64> %vecinit2
3189; P9BE-LABEL: fromDiffMemConsAll
3190; P9LE-LABEL: fromDiffMemConsAll
3191; P8BE-LABEL: fromDiffMemConsAll
3192; P8LE-LABEL: fromDiffMemConsAll
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]3193; P9BE: lxv v2
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]3194; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]3195; P9LE: lxv v2
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]3196; P9LE: blr
3197; P8BE: lxvd2x v2
3198; P8BE: blr
3199; P8LE: lxvd2x
3200; P8LE: xxswapd v2
3201; P8LE: blr
3202}
3203
3204; Function Attrs: norecurse nounwind readonly
3205define <2 x i64> @fromDiffMemConsDll(i64* nocapture readonly %arr) {
3206entry:
3207 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 3
3208 %0 = load i64, i64* %arrayidx, align 8
3209 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
3210 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 2
3211 %1 = load i64, i64* %arrayidx1, align 8
3212 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
3213 ret <2 x i64> %vecinit2
3214; P9BE-LABEL: fromDiffMemConsDll
3215; P9LE-LABEL: fromDiffMemConsDll
3216; P8BE-LABEL: fromDiffMemConsDll
3217; P8LE-LABEL: fromDiffMemConsDll
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]3218; P9BE: lxv v2
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]3219; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]3220; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]3221; P9LE: xxswapd v2
3222; P9LE: blr
3223; P8BE: lxvd2x
3224; P8BE: xxswapd v2
3225; P8BE-NEXT: blr
3226; P8LE: lxvd2x v2
3227; P8LE-NEXT: blr
3228}
3229
3230; Function Attrs: norecurse nounwind readonly
3231define <2 x i64> @fromDiffMemVarAll(i64* nocapture readonly %arr, i32 signext %elem) {
3232entry:
3233 %idxprom = sext i32 %elem to i64
3234 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom
3235 %0 = load i64, i64* %arrayidx, align 8
3236 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
3237 %add = add nsw i32 %elem, 1
3238 %idxprom1 = sext i32 %add to i64
3239 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1
3240 %1 = load i64, i64* %arrayidx2, align 8
3241 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
3242 ret <2 x i64> %vecinit3
3243; P9BE-LABEL: fromDiffMemVarAll
3244; P9LE-LABEL: fromDiffMemVarAll
3245; P8BE-LABEL: fromDiffMemVarAll
3246; P8LE-LABEL: fromDiffMemVarAll
3247; P9BE: sldi
3248; P9BE: lxvx v2
3249; P9BE-NEXT: blr
3250; P9LE: sldi
3251; P9LE: lxvx v2
3252; P9LE-NEXT: blr
3253; P8BE: sldi
3254; P8BE: lxvd2x v2
3255; P8BE-NEXT: blr
3256; P8LE: sldi
3257; P8LE: lxvd2x
3258; P8LE: xxswapd v2
3259; P8LE-NEXT: blr
3260}
3261
3262; Function Attrs: norecurse nounwind readonly
3263define <2 x i64> @fromDiffMemVarDll(i64* nocapture readonly %arr, i32 signext %elem) {
3264entry:
3265 %idxprom = sext i32 %elem to i64
3266 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom
3267 %0 = load i64, i64* %arrayidx, align 8
3268 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
3269 %sub = add nsw i32 %elem, -1
3270 %idxprom1 = sext i32 %sub to i64
3271 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1
3272 %1 = load i64, i64* %arrayidx2, align 8
3273 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
3274 ret <2 x i64> %vecinit3
3275; P9BE-LABEL: fromDiffMemVarDll
3276; P9LE-LABEL: fromDiffMemVarDll
3277; P8BE-LABEL: fromDiffMemVarDll
3278; P8LE-LABEL: fromDiffMemVarDll
3279; P9BE: sldi
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]3280; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]3281; P9BE: xxswapd v2
3282; P9BE-NEXT: blr
3283; P9LE: sldi
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]3284; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]3285; P9LE: xxswapd v2
3286; P9LE-NEXT: blr
3287; P8BE: sldi
3288; P8BE: lxvd2x
3289; P8BE: xxswapd v2
3290; P8BE-NEXT: blr
3291; P8LE: sldi
3292; P8LE: lxvd2x v2
3293; P8LE-NEXT: blr
3294}
3295
3296; Function Attrs: norecurse nounwind readonly
3297define <2 x i64> @fromRandMemConsll(i64* nocapture readonly %arr) {
3298entry:
3299 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 4
3300 %0 = load i64, i64* %arrayidx, align 8
3301 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
3302 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 18
3303 %1 = load i64, i64* %arrayidx1, align 8
3304 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
3305 ret <2 x i64> %vecinit2
3306; P9BE-LABEL: fromRandMemConsll
3307; P9LE-LABEL: fromRandMemConsll
3308; P8BE-LABEL: fromRandMemConsll
3309; P8LE-LABEL: fromRandMemConsll
3310; P9BE: ld
3311; P9BE: ld
3312; P9BE: mtvsrdd v2
3313; P9BE-NEXT: blr
3314; P9LE: ld
3315; P9LE: ld
3316; P9LE: mtvsrdd v2
3317; P9LE-NEXT: blr
3318; P8BE: ld
3319; P8BE: ld
3320; P8BE-DAG: mtvsrd
3321; P8BE-DAG: mtvsrd
3322; P8BE: xxmrghd v2
3323; P8BE-NEXT: blr
3324; P8LE: ld
3325; P8LE: ld
3326; P8LE-DAG: mtvsrd
3327; P8LE-DAG: mtvsrd
3328; P8LE: xxmrghd v2
3329; P8LE-NEXT: blr
3330}
3331
3332; Function Attrs: norecurse nounwind readonly
3333define <2 x i64> @fromRandMemVarll(i64* nocapture readonly %arr, i32 signext %elem) {
3334entry:
3335 %add = add nsw i32 %elem, 4
3336 %idxprom = sext i32 %add to i64
3337 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom
3338 %0 = load i64, i64* %arrayidx, align 8
3339 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
3340 %add1 = add nsw i32 %elem, 1
3341 %idxprom2 = sext i32 %add1 to i64
3342 %arrayidx3 = getelementptr inbounds i64, i64* %arr, i64 %idxprom2
3343 %1 = load i64, i64* %arrayidx3, align 8
3344 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
3345 ret <2 x i64> %vecinit4
3346; P9BE-LABEL: fromRandMemVarll
3347; P9LE-LABEL: fromRandMemVarll
3348; P8BE-LABEL: fromRandMemVarll
3349; P8LE-LABEL: fromRandMemVarll
3350; P9BE: sldi
3351; P9BE: ld
3352; P9BE: ld
3353; P9BE: mtvsrdd v2
3354; P9BE-NEXT: blr
3355; P9LE: sldi
3356; P9LE: ld
3357; P9LE: ld
3358; P9LE: mtvsrdd v2
3359; P9LE-NEXT: blr
3360; P8BE: sldi
3361; P8BE: ld
3362; P8BE: ld
3363; P8BE: mtvsrd
3364; P8BE: mtvsrd
3365; P8BE: xxmrghd v2
3366; P8BE-NEXT: blr
3367; P8LE: sldi
3368; P8LE: ld
3369; P8LE: ld
3370; P8LE: mtvsrd
3371; P8LE: mtvsrd
3372; P8LE: xxmrghd v2
3373; P8LE-NEXT: blr
3374}
3375
3376; Function Attrs: norecurse nounwind readnone
3377define <2 x i64> @spltRegValll(i64 %val) {
3378entry:
3379 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0
3380 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
3381 ret <2 x i64> %splat.splat
3382; P9BE-LABEL: spltRegValll
3383; P9LE-LABEL: spltRegValll
3384; P8BE-LABEL: spltRegValll
3385; P8LE-LABEL: spltRegValll
3386; P9BE: mtvsrdd v2, r3, r3
3387; P9BE-NEXT: blr
3388; P9LE: mtvsrdd v2, r3, r3
3389; P9LE-NEXT: blr
3390; P8BE: mtvsrd {{[vsf]+}}[[REG1:[0-9]+]], r3
3391; P8BE: xxspltd v2, {{[vsf]+}}[[REG1]], 0
3392; P8BE-NEXT: blr
3393; P8LE: mtvsrd {{[vsf]+}}[[REG1:[0-9]+]], r3
3394; P8LE: xxspltd v2, {{[vsf]+}}[[REG1]], 0
3395; P8LE-NEXT: blr
3396}
3397
3398; Function Attrs: norecurse nounwind readonly
3399define <2 x i64> @spltMemValll(i64* nocapture readonly %ptr) {
3400entry:
3401 %0 = load i64, i64* %ptr, align 8
3402 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0
3403 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
3404 ret <2 x i64> %splat.splat
3405; P9BE-LABEL: spltMemValll
3406; P9LE-LABEL: spltMemValll
3407; P8BE-LABEL: spltMemValll
3408; P8LE-LABEL: spltMemValll
3409; P9BE: lxvdsx v2
3410; P9BE-NEXT: blr
3411; P9LE: lxvdsx v2
3412; P9LE-NEXT: blr
3413; P8BE: lxvdsx v2
3414; P8BE-NEXT: blr
3415; P8LE: lxvdsx v2
3416; P8LE-NEXT: blr
3417}
3418
3419; Function Attrs: norecurse nounwind readnone
3420define <2 x i64> @spltCnstConvftoll() {
3421entry:
3422 ret <2 x i64> <i64 4, i64 4>
3423; P9BE-LABEL: spltCnstConvftoll
3424; P9LE-LABEL: spltCnstConvftoll
3425; P8BE-LABEL: spltCnstConvftoll
3426; P8LE-LABEL: spltCnstConvftoll
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]3427; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]3428; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]3429; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]3430; P9LE: blr
3431; P8BE: lxvd2x
3432; P8BE: blr
3433; P8LE: lxvd2x
3434; P8LE: blr
3435}
3436
3437; Function Attrs: norecurse nounwind readnone
3438define <2 x i64> @fromRegsConvftoll(float %a, float %b) {
3439entry:
3440 %conv = fptosi float %a to i64
3441 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
3442 %conv1 = fptosi float %b to i64
3443 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1
3444 ret <2 x i64> %vecinit2
3445; P9BE-LABEL: fromRegsConvftoll
3446; P9LE-LABEL: fromRegsConvftoll
3447; P8BE-LABEL: fromRegsConvftoll
3448; P8LE-LABEL: fromRegsConvftoll
3449; P9BE: xxmrghd
3450; P9BE: xvcvdpsxds v2
3451; P9BE-NEXT: blr
3452; P9LE: xxmrghd
3453; P9LE: xvcvdpsxds v2
3454; P9LE-NEXT: blr
3455; P8BE: xxmrghd
3456; P8BE: xvcvdpsxds v2
3457; P8BE-NEXT: blr
3458; P8LE: xxmrghd
3459; P8LE: xvcvdpsxds v2
3460; P8LE-NEXT: blr
3461}
3462
3463; Function Attrs: norecurse nounwind readnone
3464define <2 x i64> @fromDiffConstsConvftoll() {
3465entry:
3466 ret <2 x i64> <i64 24, i64 234>
3467; P9BE-LABEL: fromDiffConstsConvftoll
3468; P9LE-LABEL: fromDiffConstsConvftoll
3469; P8BE-LABEL: fromDiffConstsConvftoll
3470; P8LE-LABEL: fromDiffConstsConvftoll
Nemanja Ivanovic3c7e276d2017-07-13 18:17:10 +0000[diff] [blame^]3471; P9BE: lxvx v2
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]3472; P9BE: blr
Nemanja Ivanovic3c7e276d2017-07-13 18:17:10 +0000[diff] [blame^]3473; P9LE: lxvx v2
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]3474; P9LE: blr
3475; P8BE: lxvd2x v2
3476; P8BE: blr
3477; P8LE: lxvd2x
3478; P8LE: xxswapd v2
3479; P8LE: blr
3480}
3481
3482; Function Attrs: norecurse nounwind readonly
3483define <2 x i64> @fromDiffMemConsAConvftoll(float* nocapture readonly %ptr) {
3484entry:
3485 %0 = load float, float* %ptr, align 4
3486 %conv = fptosi float %0 to i64
3487 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
3488 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 1
3489 %1 = load float, float* %arrayidx1, align 4
3490 %conv2 = fptosi float %1 to i64
3491 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
3492 ret <2 x i64> %vecinit3
3493; P9BE-LABEL: fromDiffMemConsAConvftoll
3494; P9LE-LABEL: fromDiffMemConsAConvftoll
3495; P8BE-LABEL: fromDiffMemConsAConvftoll
3496; P8LE-LABEL: fromDiffMemConsAConvftoll
3497; P9BE: lfs
3498; P9BE: lfs
3499; P9BE: xxmrghd
3500; P9BE-NEXT: xvcvdpsxds v2
3501; P9BE-NEXT: blr
3502; P9LE: lfs
3503; P9LE: lfs
3504; P9LE: xxmrghd
3505; P9LE-NEXT: xvcvdpsxds v2
3506; P9LE-NEXT: blr
3507; P8BE: lxsspx
3508; P8BE: lxsspx
3509; P8BE: xxmrghd
3510; P8BE-NEXT: xvcvdpsxds v2
3511; P8BE-NEXT: blr
3512; P8LE: lxsspx
3513; P8LE: lxsspx
3514; P8LE: xxmrghd
3515; P8LE-NEXT: xvcvdpsxds v2
3516; P8LE-NEXT: blr
3517}
3518
3519; Function Attrs: norecurse nounwind readonly
3520define <2 x i64> @fromDiffMemConsDConvftoll(float* nocapture readonly %ptr) {
3521entry:
3522 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3
3523 %0 = load float, float* %arrayidx, align 4
3524 %conv = fptosi float %0 to i64
3525 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
3526 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2
3527 %1 = load float, float* %arrayidx1, align 4
3528 %conv2 = fptosi float %1 to i64
3529 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
3530 ret <2 x i64> %vecinit3
3531; P9BE-LABEL: fromDiffMemConsDConvftoll
3532; P9LE-LABEL: fromDiffMemConsDConvftoll
3533; P8BE-LABEL: fromDiffMemConsDConvftoll
3534; P8LE-LABEL: fromDiffMemConsDConvftoll
3535; P9BE: lfs
3536; P9BE: lfs
3537; P9BE: xxmrghd
3538; P9BE-NEXT: xvcvdpsxds v2
3539; P9BE-NEXT: blr
3540; P9LE: lfs
3541; P9LE: lfs
3542; P9LE: xxmrghd
3543; P9LE-NEXT: xvcvdpsxds v2
3544; P9LE-NEXT: blr
3545; P8BE: lxsspx
3546; P8BE: lxsspx
3547; P8BE: xxmrghd
3548; P8BE-NEXT: xvcvdpsxds v2
3549; P8BE-NEXT: blr
3550; P8LE: lxsspx
3551; P8LE: lxsspx
3552; P8LE: xxmrghd
3553; P8LE-NEXT: xvcvdpsxds v2
3554; P8LE-NEXT: blr
3555}
3556
3557; Function Attrs: norecurse nounwind readonly
3558define <2 x i64> @fromDiffMemVarAConvftoll(float* nocapture readonly %arr, i32 signext %elem) {
3559entry:
3560 %idxprom = sext i32 %elem to i64
3561 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom
3562 %0 = load float, float* %arrayidx, align 4
3563 %conv = fptosi float %0 to i64
3564 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
3565 %add = add nsw i32 %elem, 1
3566 %idxprom1 = sext i32 %add to i64
3567 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1
3568 %1 = load float, float* %arrayidx2, align 4
3569 %conv3 = fptosi float %1 to i64
3570 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
3571 ret <2 x i64> %vecinit4
3572; P9BE-LABEL: fromDiffMemVarAConvftoll
3573; P9LE-LABEL: fromDiffMemVarAConvftoll
3574; P8BE-LABEL: fromDiffMemVarAConvftoll
3575; P8LE-LABEL: fromDiffMemVarAConvftoll
3576; P9BE: sldi
3577; P9BE: lfsux
3578; P9BE: lfs
3579; P9BE: xxmrghd
3580; P9BE-NEXT: xvcvdpsxds v2
3581; P9BE-NEXT: blr
3582; P9LE: sldi
3583; P9LE: lfsux
3584; P9LE: lfs
3585; P9LE: xxmrghd
3586; P9LE-NEXT: xvcvdpsxds v2
3587; P9LE-NEXT: blr
3588; P8BE: sldi
3589; P8BE: lfsux
3590; P8BE: lxsspx
3591; P8BE: xxmrghd
3592; P8BE-NEXT: xvcvdpsxds v2
3593; P8BE-NEXT: blr
3594; P8LE: sldi
3595; P8LE: lfsux
3596; P8LE: lxsspx
3597; P8LE: xxmrghd
3598; P8LE-NEXT: xvcvdpsxds v2
3599; P8LE-NEXT: blr
3600}
3601
3602; Function Attrs: norecurse nounwind readonly
3603define <2 x i64> @fromDiffMemVarDConvftoll(float* nocapture readonly %arr, i32 signext %elem) {
3604entry:
3605 %idxprom = sext i32 %elem to i64
3606 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom
3607 %0 = load float, float* %arrayidx, align 4
3608 %conv = fptosi float %0 to i64
3609 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
3610 %sub = add nsw i32 %elem, -1
3611 %idxprom1 = sext i32 %sub to i64
3612 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1
3613 %1 = load float, float* %arrayidx2, align 4
3614 %conv3 = fptosi float %1 to i64
3615 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
3616 ret <2 x i64> %vecinit4
3617; P9BE-LABEL: fromDiffMemVarDConvftoll
3618; P9LE-LABEL: fromDiffMemVarDConvftoll
3619; P8BE-LABEL: fromDiffMemVarDConvftoll
3620; P8LE-LABEL: fromDiffMemVarDConvftoll
3621; P9BE: sldi
3622; P9BE: lfsux
3623; P9BE: lfs
3624; P9BE: xxmrghd
3625; P9BE-NEXT: xvcvdpsxds v2
3626; P9BE-NEXT: blr
3627; P9LE: sldi
3628; P9LE: lfsux
3629; P9LE: lfs
3630; P9LE: xxmrghd
3631; P9LE-NEXT: xvcvdpsxds v2
3632; P9LE-NEXT: blr
3633; P8BE: sldi
3634; P8BE: lfsux
3635; P8BE: lxsspx
3636; P8BE: xxmrghd
3637; P8BE-NEXT: xvcvdpsxds v2
3638; P8BE-NEXT: blr
3639; P8LE: sldi
3640; P8LE: lfsux
3641; P8LE: lxsspx
3642; P8LE: xxmrghd
3643; P8LE-NEXT: xvcvdpsxds v2
3644; P8LE-NEXT: blr
3645}
3646
3647; Function Attrs: norecurse nounwind readnone
3648define <2 x i64> @spltRegValConvftoll(float %val) {
3649entry:
3650 %conv = fptosi float %val to i64
3651 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
3652 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
3653 ret <2 x i64> %splat.splat
3654; P9BE-LABEL: spltRegValConvftoll
3655; P9LE-LABEL: spltRegValConvftoll
3656; P8BE-LABEL: spltRegValConvftoll
3657; P8LE-LABEL: spltRegValConvftoll
3658; P9BE: xscvdpsxds
3659; P9BE-NEXT: xxspltd v2
3660; P9BE-NEXT: blr
3661; P9LE: xscvdpsxds
3662; P9LE-NEXT: xxspltd v2
3663; P9LE-NEXT: blr
3664; P8BE: xscvdpsxds
3665; P8BE-NEXT: xxspltd v2
3666; P8BE-NEXT: blr
3667; P8LE: xscvdpsxds
3668; P8LE-NEXT: xxspltd v2
3669; P8LE-NEXT: blr
3670}
3671
3672; Function Attrs: norecurse nounwind readonly
3673define <2 x i64> @spltMemValConvftoll(float* nocapture readonly %ptr) {
3674entry:
3675 %0 = load float, float* %ptr, align 4
3676 %conv = fptosi float %0 to i64
3677 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
3678 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
3679 ret <2 x i64> %splat.splat
3680; P9BE-LABEL: spltMemValConvftoll
3681; P9LE-LABEL: spltMemValConvftoll
3682; P8BE-LABEL: spltMemValConvftoll
3683; P8LE-LABEL: spltMemValConvftoll
3684; P9BE: lfs
3685; P9BE-NEXT: xscvdpsxds
3686; P9BE-NEXT: xxspltd v2
3687; P9BE-NEXT: blr
3688; P9LE: lfs
3689; P9LE-NEXT: xscvdpsxds
3690; P9LE-NEXT: xxspltd v2
3691; P9LE-NEXT: blr
3692; P8BE: lxsspx
3693; P8BE-NEXT: xscvdpsxds
3694; P8BE-NEXT: xxspltd v2
3695; P8BE-NEXT: blr
3696; P8LE: lxsspx
3697; P8LE-NEXT: xscvdpsxds
3698; P8LE-NEXT: xxspltd v2
3699; P8LE-NEXT: blr
3700}
3701
3702; Function Attrs: norecurse nounwind readnone
3703define <2 x i64> @spltCnstConvdtoll() {
3704entry:
3705 ret <2 x i64> <i64 4, i64 4>
3706; P9BE-LABEL: spltCnstConvdtoll
3707; P9LE-LABEL: spltCnstConvdtoll
3708; P8BE-LABEL: spltCnstConvdtoll
3709; P8LE-LABEL: spltCnstConvdtoll
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]3710; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]3711; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]3712; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]3713; P9LE: blr
3714; P8BE: lxvd2x
3715; P8BE: blr
3716; P8LE: lxvd2x
3717; P8LE: blr
3718}
3719
3720; Function Attrs: norecurse nounwind readnone
3721define <2 x i64> @fromRegsConvdtoll(double %a, double %b) {
3722entry:
3723 %conv = fptosi double %a to i64
3724 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
3725 %conv1 = fptosi double %b to i64
3726 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1
3727 ret <2 x i64> %vecinit2
3728; P9BE-LABEL: fromRegsConvdtoll
3729; P9LE-LABEL: fromRegsConvdtoll
3730; P8BE-LABEL: fromRegsConvdtoll
3731; P8LE-LABEL: fromRegsConvdtoll
3732; P9BE: xxmrghd
3733; P9BE-NEXT: xvcvdpsxds
3734; P9BE-NEXT: blr
3735; P9LE: xxmrghd
3736; P9LE-NEXT: xvcvdpsxds
3737; P9LE-NEXT: blr
3738; P8BE: xxmrghd
3739; P8BE-NEXT: xvcvdpsxds
3740; P8BE-NEXT: blr
3741; P8LE: xxmrghd
3742; P8LE-NEXT: xvcvdpsxds
3743; P8LE-NEXT: blr
3744}
3745
3746; Function Attrs: norecurse nounwind readnone
3747define <2 x i64> @fromDiffConstsConvdtoll() {
3748entry:
3749 ret <2 x i64> <i64 24, i64 234>
3750; P9BE-LABEL: fromDiffConstsConvdtoll
3751; P9LE-LABEL: fromDiffConstsConvdtoll
3752; P8BE-LABEL: fromDiffConstsConvdtoll
3753; P8LE-LABEL: fromDiffConstsConvdtoll
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]3754; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]3755; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]3756; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]3757; P9LE: blr
3758; P8BE: lxvd2x
3759; P8BE: blr
3760; P8LE: lxvd2x
3761; P8LE: blr
3762}
3763
3764; Function Attrs: norecurse nounwind readonly
3765define <2 x i64> @fromDiffMemConsAConvdtoll(double* nocapture readonly %ptr) {
3766entry:
3767 %0 = bitcast double* %ptr to <2 x double>*
3768 %1 = load <2 x double>, <2 x double>* %0, align 8
3769 %2 = fptosi <2 x double> %1 to <2 x i64>
3770 ret <2 x i64> %2
3771; P9BE-LABEL: fromDiffMemConsAConvdtoll
3772; P9LE-LABEL: fromDiffMemConsAConvdtoll
3773; P8BE-LABEL: fromDiffMemConsAConvdtoll
3774; P8LE-LABEL: fromDiffMemConsAConvdtoll
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]3775; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]3776; P9BE-NEXT: xvcvdpsxds v2
3777; P9BE-NEXT: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]3778; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]3779; P9LE-NEXT: xvcvdpsxds v2
3780; P9LE-NEXT: blr
3781; P8BE: lxvd2x
3782; P8BE-NEXT: xvcvdpsxds v2
3783; P8BE-NEXT: blr
3784; P8LE: lxvd2x
3785; P8LE: xxswapd
3786; P8LE-NEXT: xvcvdpsxds v2
3787; P8LE-NEXT: blr
3788}
3789
3790; Function Attrs: norecurse nounwind readonly
3791define <2 x i64> @fromDiffMemConsDConvdtoll(double* nocapture readonly %ptr) {
3792entry:
3793 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3
3794 %0 = load double, double* %arrayidx, align 8
3795 %conv = fptosi double %0 to i64
3796 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
3797 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2
3798 %1 = load double, double* %arrayidx1, align 8
3799 %conv2 = fptosi double %1 to i64
3800 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
3801 ret <2 x i64> %vecinit3
3802; P9BE-LABEL: fromDiffMemConsDConvdtoll
3803; P9LE-LABEL: fromDiffMemConsDConvdtoll
3804; P8BE-LABEL: fromDiffMemConsDConvdtoll
3805; P8LE-LABEL: fromDiffMemConsDConvdtoll
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]3806; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]3807; P9BE-NEXT: xxswapd
3808; P9BE-NEXT: xvcvdpsxds v2
3809; P9BE-NEXT: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]3810; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]3811; P9LE-NEXT: xxswapd
3812; P9LE-NEXT: xvcvdpsxds v2
3813; P9LE-NEXT: blr
3814; P8BE: lxvd2x
3815; P8BE-NEXT: xxswapd
3816; P8BE-NEXT: xvcvdpsxds v2
3817; P8BE-NEXT: blr
3818; P8LE: lxvd2x
3819; P8LE-NEXT: xvcvdpsxds v2
3820; P8LE-NEXT: blr
3821}
3822
3823; Function Attrs: norecurse nounwind readonly
3824define <2 x i64> @fromDiffMemVarAConvdtoll(double* nocapture readonly %arr, i32 signext %elem) {
3825entry:
3826 %idxprom = sext i32 %elem to i64
3827 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom
3828 %0 = load double, double* %arrayidx, align 8
3829 %conv = fptosi double %0 to i64
3830 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
3831 %add = add nsw i32 %elem, 1
3832 %idxprom1 = sext i32 %add to i64
3833 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1
3834 %1 = load double, double* %arrayidx2, align 8
3835 %conv3 = fptosi double %1 to i64
3836 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
3837 ret <2 x i64> %vecinit4
3838; P9BE-LABEL: fromDiffMemVarAConvdtoll
3839; P9LE-LABEL: fromDiffMemVarAConvdtoll
3840; P8BE-LABEL: fromDiffMemVarAConvdtoll
3841; P8LE-LABEL: fromDiffMemVarAConvdtoll
3842; P9BE: sldi
3843; P9BE: lxvx
3844; P9BE-NEXT: xvcvdpsxds v2
3845; P9BE-NEXT: blr
3846; P9LE: sldi
3847; P9LE: lxvx
3848; P9LE-NEXT: xvcvdpsxds v2
3849; P9LE-NEXT: blr
3850; P8BE: sldi
3851; P8BE: lxvd2x
3852; P8BE-NEXT: xvcvdpsxds v2
3853; P8BE-NEXT: blr
3854; P8LE: sldi
3855; P8LE: lxvd2x
3856; P8LE-NEXT: xxswapd
3857; P8LE-NEXT: xvcvdpsxds v2
3858; P8LE-NEXT: blr
3859}
3860
3861; Function Attrs: norecurse nounwind readonly
3862define <2 x i64> @fromDiffMemVarDConvdtoll(double* nocapture readonly %arr, i32 signext %elem) {
3863entry:
3864 %idxprom = sext i32 %elem to i64
3865 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom
3866 %0 = load double, double* %arrayidx, align 8
3867 %conv = fptosi double %0 to i64
3868 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
3869 %sub = add nsw i32 %elem, -1
3870 %idxprom1 = sext i32 %sub to i64
3871 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1
3872 %1 = load double, double* %arrayidx2, align 8
3873 %conv3 = fptosi double %1 to i64
3874 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
3875 ret <2 x i64> %vecinit4
3876; P9BE-LABEL: fromDiffMemVarDConvdtoll
3877; P9LE-LABEL: fromDiffMemVarDConvdtoll
3878; P8BE-LABEL: fromDiffMemVarDConvdtoll
3879; P8LE-LABEL: fromDiffMemVarDConvdtoll
3880; P9BE: sldi
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]3881; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]3882; P9BE-NEXT: xxswapd
3883; P9BE-NEXT: xvcvdpsxds v2
3884; P9BE-NEXT: blr
3885; P9LE: sldi
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]3886; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]3887; P9LE-NEXT: xxswapd
3888; P9LE-NEXT: xvcvdpsxds v2
3889; P9LE-NEXT: blr
3890; P8BE: sldi
3891; P8BE: lxvd2x
3892; P8BE-NEXT: xxswapd
3893; P8BE-NEXT: xvcvdpsxds v2
3894; P8BE-NEXT: blr
3895; P8LE: sldi
3896; P8LE: lxvd2x
3897; P8LE-NEXT: xvcvdpsxds v2
3898; P8LE-NEXT: blr
3899}
3900
3901; Function Attrs: norecurse nounwind readnone
3902define <2 x i64> @spltRegValConvdtoll(double %val) {
3903entry:
3904 %conv = fptosi double %val to i64
3905 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
3906 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
3907 ret <2 x i64> %splat.splat
3908; P9BE-LABEL: spltRegValConvdtoll
3909; P9LE-LABEL: spltRegValConvdtoll
3910; P8BE-LABEL: spltRegValConvdtoll
3911; P8LE-LABEL: spltRegValConvdtoll
3912; P9BE: xscvdpsxds
3913; P9BE-NEXT: xxspltd v2
3914; P9BE-NEXT: blr
3915; P9LE: xscvdpsxds
3916; P9LE-NEXT: xxspltd v2
3917; P9LE-NEXT: blr
3918; P8BE: xscvdpsxds
3919; P8BE-NEXT: xxspltd v2
3920; P8BE-NEXT: blr
3921; P8LE: xscvdpsxds
3922; P8LE-NEXT: xxspltd v2
3923; P8LE-NEXT: blr
3924}
3925
3926; Function Attrs: norecurse nounwind readonly
3927define <2 x i64> @spltMemValConvdtoll(double* nocapture readonly %ptr) {
3928entry:
3929 %0 = load double, double* %ptr, align 8
3930 %conv = fptosi double %0 to i64
3931 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
3932 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
3933 ret <2 x i64> %splat.splat
3934; P9BE-LABEL: spltMemValConvdtoll
3935; P9LE-LABEL: spltMemValConvdtoll
3936; P8BE-LABEL: spltMemValConvdtoll
3937; P8LE-LABEL: spltMemValConvdtoll
3938; P9BE: lxvdsx
3939; P9BE-NEXT: xvcvdpsxds
3940; P9BE-NEXT: blr
3941; P9LE: lxvdsx
3942; P9LE-NEXT: xvcvdpsxds
3943; P9LE-NEXT: blr
3944; P8BE: lxvdsx
3945; P8BE-NEXT: xvcvdpsxds
3946; P8BE-NEXT: blr
3947; P8LE: lxvdsx
3948; P8LE-NEXT: xvcvdpsxds
3949; P8LE-NEXT: blr
3950}
3951
3952; Function Attrs: norecurse nounwind readnone
3953define <2 x i64> @allZeroull() {
3954entry:
3955 ret <2 x i64> zeroinitializer
3956; P9BE-LABEL: allZeroull
3957; P9LE-LABEL: allZeroull
3958; P8BE-LABEL: allZeroull
3959; P8LE-LABEL: allZeroull
3960; P9BE: xxlxor v2, v2, v2
3961; P9BE: blr
3962; P9LE: xxlxor v2, v2, v2
3963; P9LE: blr
3964; P8BE: xxlxor v2, v2, v2
3965; P8BE: blr
3966; P8LE: xxlxor v2, v2, v2
3967; P8LE: blr
3968}
3969
3970; Function Attrs: norecurse nounwind readnone
3971define <2 x i64> @allOneull() {
3972entry:
3973 ret <2 x i64> <i64 -1, i64 -1>
3974; P9BE-LABEL: allOneull
3975; P9LE-LABEL: allOneull
3976; P8BE-LABEL: allOneull
3977; P8LE-LABEL: allOneull
3978; P9BE: xxspltib v2, 255
3979; P9BE: blr
3980; P9LE: xxspltib v2, 255
3981; P9LE: blr
3982; P8BE: vspltisb v2, -1
3983; P8BE: blr
3984; P8LE: vspltisb v2, -1
3985; P8LE: blr
3986}
3987
3988; Function Attrs: norecurse nounwind readnone
3989define <2 x i64> @spltConst1ull() {
3990entry:
3991 ret <2 x i64> <i64 1, i64 1>
3992; P9BE-LABEL: spltConst1ull
3993; P9LE-LABEL: spltConst1ull
3994; P8BE-LABEL: spltConst1ull
3995; P8LE-LABEL: spltConst1ull
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]3996; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]3997; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]3998; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]3999; P9LE: blr
4000; P8BE: lxvd2x
4001; P8BE: blr
4002; P8LE: lxvd2x
4003; P8LE: blr
4004}
4005
4006; Function Attrs: norecurse nounwind readnone
4007define <2 x i64> @spltConst16kull() {
4008entry:
4009 ret <2 x i64> <i64 32767, i64 32767>
4010; P9BE-LABEL: spltConst16kull
4011; P9LE-LABEL: spltConst16kull
4012; P8BE-LABEL: spltConst16kull
4013; P8LE-LABEL: spltConst16kull
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]4014; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]4015; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]4016; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]4017; P9LE: blr
4018; P8BE: lxvd2x
4019; P8BE: blr
4020; P8LE: lxvd2x
4021; P8LE: blr
4022}
4023
4024; Function Attrs: norecurse nounwind readnone
4025define <2 x i64> @spltConst32kull() {
4026entry:
4027 ret <2 x i64> <i64 65535, i64 65535>
4028; P9BE-LABEL: spltConst32kull
4029; P9LE-LABEL: spltConst32kull
4030; P8BE-LABEL: spltConst32kull
4031; P8LE-LABEL: spltConst32kull
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]4032; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]4033; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]4034; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]4035; P9LE: blr
4036; P8BE: lxvd2x
4037; P8BE: blr
4038; P8LE: lxvd2x
4039; P8LE: blr
4040}
4041
4042; Function Attrs: norecurse nounwind readnone
4043define <2 x i64> @fromRegsull(i64 %a, i64 %b) {
4044entry:
4045 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0
4046 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1
4047 ret <2 x i64> %vecinit1
4048; P9BE-LABEL: fromRegsull
4049; P9LE-LABEL: fromRegsull
4050; P8BE-LABEL: fromRegsull
4051; P8LE-LABEL: fromRegsull
4052; P9BE: mtvsrdd v2, r3, r4
4053; P9BE: blr
4054; P9LE: mtvsrdd v2, r4, r3
4055; P9LE: blr
4056; P8BE-DAG: mtvsrd {{[vsf0-9]+}}, r3
4057; P8BE-DAG: mtvsrd {{[vsf0-9]+}}, r4
4058; P8BE: xxmrghd v2
4059; P8BE: blr
4060; P8LE-DAG: mtvsrd {{[vsf0-9]+}}, r3
4061; P8LE-DAG: mtvsrd {{[vsf0-9]+}}, r4
4062; P8LE: xxmrghd v2
4063; P8LE: blr
4064}
4065
4066; Function Attrs: norecurse nounwind readnone
4067define <2 x i64> @fromDiffConstsull() {
4068entry:
4069 ret <2 x i64> <i64 242, i64 -113>
4070; P9BE-LABEL: fromDiffConstsull
4071; P9LE-LABEL: fromDiffConstsull
4072; P8BE-LABEL: fromDiffConstsull
4073; P8LE-LABEL: fromDiffConstsull
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]4074; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]4075; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]4076; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]4077; P9LE: blr
4078; P8BE: lxvd2x
4079; P8BE: blr
4080; P8LE: lxvd2x
4081; P8LE: blr
4082}
4083
4084; Function Attrs: norecurse nounwind readonly
4085define <2 x i64> @fromDiffMemConsAull(i64* nocapture readonly %arr) {
4086entry:
4087 %0 = load i64, i64* %arr, align 8
4088 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
4089 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 1
4090 %1 = load i64, i64* %arrayidx1, align 8
4091 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
4092 ret <2 x i64> %vecinit2
4093; P9BE-LABEL: fromDiffMemConsAull
4094; P9LE-LABEL: fromDiffMemConsAull
4095; P8BE-LABEL: fromDiffMemConsAull
4096; P8LE-LABEL: fromDiffMemConsAull
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]4097; P9BE: lxv v2
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]4098; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]4099; P9LE: lxv v2
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]4100; P9LE: blr
4101; P8BE: lxvd2x v2
4102; P8BE: blr
4103; P8LE: lxvd2x
4104; P8LE: xxswapd v2
4105; P8LE: blr
4106}
4107
4108; Function Attrs: norecurse nounwind readonly
4109define <2 x i64> @fromDiffMemConsDull(i64* nocapture readonly %arr) {
4110entry:
4111 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 3
4112 %0 = load i64, i64* %arrayidx, align 8
4113 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
4114 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 2
4115 %1 = load i64, i64* %arrayidx1, align 8
4116 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
4117 ret <2 x i64> %vecinit2
4118; P9BE-LABEL: fromDiffMemConsDull
4119; P9LE-LABEL: fromDiffMemConsDull
4120; P8BE-LABEL: fromDiffMemConsDull
4121; P8LE-LABEL: fromDiffMemConsDull
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]4122; P9BE: lxv v2
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]4123; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]4124; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]4125; P9LE: xxswapd v2
4126; P9LE: blr
4127; P8BE: lxvd2x
4128; P8BE: xxswapd v2
4129; P8BE-NEXT: blr
4130; P8LE: lxvd2x v2
4131; P8LE-NEXT: blr
4132}
4133
4134; Function Attrs: norecurse nounwind readonly
4135define <2 x i64> @fromDiffMemVarAull(i64* nocapture readonly %arr, i32 signext %elem) {
4136entry:
4137 %idxprom = sext i32 %elem to i64
4138 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom
4139 %0 = load i64, i64* %arrayidx, align 8
4140 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
4141 %add = add nsw i32 %elem, 1
4142 %idxprom1 = sext i32 %add to i64
4143 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1
4144 %1 = load i64, i64* %arrayidx2, align 8
4145 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
4146 ret <2 x i64> %vecinit3
4147; P9BE-LABEL: fromDiffMemVarAull
4148; P9LE-LABEL: fromDiffMemVarAull
4149; P8BE-LABEL: fromDiffMemVarAull
4150; P8LE-LABEL: fromDiffMemVarAull
4151; P9BE: sldi
4152; P9BE: lxvx v2
4153; P9BE-NEXT: blr
4154; P9LE: sldi
4155; P9LE: lxvx v2
4156; P9LE-NEXT: blr
4157; P8BE: sldi
4158; P8BE: lxvd2x v2
4159; P8BE-NEXT: blr
4160; P8LE: sldi
4161; P8LE: lxvd2x
4162; P8LE: xxswapd v2
4163; P8LE-NEXT: blr
4164}
4165
4166; Function Attrs: norecurse nounwind readonly
4167define <2 x i64> @fromDiffMemVarDull(i64* nocapture readonly %arr, i32 signext %elem) {
4168entry:
4169 %idxprom = sext i32 %elem to i64
4170 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom
4171 %0 = load i64, i64* %arrayidx, align 8
4172 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
4173 %sub = add nsw i32 %elem, -1
4174 %idxprom1 = sext i32 %sub to i64
4175 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1
4176 %1 = load i64, i64* %arrayidx2, align 8
4177 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
4178 ret <2 x i64> %vecinit3
4179; P9BE-LABEL: fromDiffMemVarDull
4180; P9LE-LABEL: fromDiffMemVarDull
4181; P8BE-LABEL: fromDiffMemVarDull
4182; P8LE-LABEL: fromDiffMemVarDull
4183; P9BE: sldi
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]4184; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]4185; P9BE: xxswapd v2
4186; P9BE-NEXT: blr
4187; P9LE: sldi
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]4188; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]4189; P9LE: xxswapd v2
4190; P9LE-NEXT: blr
4191; P8BE: sldi
4192; P8BE: lxvd2x
4193; P8BE: xxswapd v2
4194; P8BE-NEXT: blr
4195; P8LE: sldi
4196; P8LE: lxvd2x v2
4197; P8LE-NEXT: blr
4198}
4199
4200; Function Attrs: norecurse nounwind readonly
4201define <2 x i64> @fromRandMemConsull(i64* nocapture readonly %arr) {
4202entry:
4203 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 4
4204 %0 = load i64, i64* %arrayidx, align 8
4205 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
4206 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 18
4207 %1 = load i64, i64* %arrayidx1, align 8
4208 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
4209 ret <2 x i64> %vecinit2
4210; P9BE-LABEL: fromRandMemConsull
4211; P9LE-LABEL: fromRandMemConsull
4212; P8BE-LABEL: fromRandMemConsull
4213; P8LE-LABEL: fromRandMemConsull
4214; P9BE: ld
4215; P9BE: ld
4216; P9BE: mtvsrdd v2
4217; P9BE-NEXT: blr
4218; P9LE: ld
4219; P9LE: ld
4220; P9LE: mtvsrdd v2
4221; P9LE-NEXT: blr
4222; P8BE: ld
4223; P8BE: ld
4224; P8BE-DAG: mtvsrd
4225; P8BE-DAG: mtvsrd
4226; P8BE: xxmrghd v2
4227; P8BE-NEXT: blr
4228; P8LE: ld
4229; P8LE: ld
4230; P8LE-DAG: mtvsrd
4231; P8LE-DAG: mtvsrd
4232; P8LE: xxmrghd v2
4233; P8LE-NEXT: blr
4234}
4235
4236; Function Attrs: norecurse nounwind readonly
4237define <2 x i64> @fromRandMemVarull(i64* nocapture readonly %arr, i32 signext %elem) {
4238entry:
4239 %add = add nsw i32 %elem, 4
4240 %idxprom = sext i32 %add to i64
4241 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom
4242 %0 = load i64, i64* %arrayidx, align 8
4243 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
4244 %add1 = add nsw i32 %elem, 1
4245 %idxprom2 = sext i32 %add1 to i64
4246 %arrayidx3 = getelementptr inbounds i64, i64* %arr, i64 %idxprom2
4247 %1 = load i64, i64* %arrayidx3, align 8
4248 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
4249 ret <2 x i64> %vecinit4
4250; P9BE-LABEL: fromRandMemVarull
4251; P9LE-LABEL: fromRandMemVarull
4252; P8BE-LABEL: fromRandMemVarull
4253; P8LE-LABEL: fromRandMemVarull
4254; P9BE: sldi
4255; P9BE: ld
4256; P9BE: ld
4257; P9BE: mtvsrdd v2
4258; P9BE-NEXT: blr
4259; P9LE: sldi
4260; P9LE: ld
4261; P9LE: ld
4262; P9LE: mtvsrdd v2
4263; P9LE-NEXT: blr
4264; P8BE: sldi
4265; P8BE: ld
4266; P8BE: ld
4267; P8BE: mtvsrd
4268; P8BE: mtvsrd
4269; P8BE: xxmrghd v2
4270; P8BE-NEXT: blr
4271; P8LE: sldi
4272; P8LE: ld
4273; P8LE: ld
4274; P8LE: mtvsrd
4275; P8LE: mtvsrd
4276; P8LE: xxmrghd v2
4277; P8LE-NEXT: blr
4278}
4279
4280; Function Attrs: norecurse nounwind readnone
4281define <2 x i64> @spltRegValull(i64 %val) {
4282entry:
4283 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0
4284 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
4285 ret <2 x i64> %splat.splat
4286; P9BE-LABEL: spltRegValull
4287; P9LE-LABEL: spltRegValull
4288; P8BE-LABEL: spltRegValull
4289; P8LE-LABEL: spltRegValull
4290; P9BE: mtvsrdd v2, r3, r3
4291; P9BE-NEXT: blr
4292; P9LE: mtvsrdd v2, r3, r3
4293; P9LE-NEXT: blr
4294; P8BE: mtvsrd {{[vsf]+}}[[REG1:[0-9]+]], r3
4295; P8BE: xxspltd v2, {{[vsf]+}}[[REG1]], 0
4296; P8BE-NEXT: blr
4297; P8LE: mtvsrd {{[vsf]+}}[[REG1:[0-9]+]], r3
4298; P8LE: xxspltd v2, {{[vsf]+}}[[REG1]], 0
4299; P8LE-NEXT: blr
4300}
4301
4302; Function Attrs: norecurse nounwind readonly
4303define <2 x i64> @spltMemValull(i64* nocapture readonly %ptr) {
4304entry:
4305 %0 = load i64, i64* %ptr, align 8
4306 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0
4307 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
4308 ret <2 x i64> %splat.splat
4309; P9BE-LABEL: spltMemValull
4310; P9LE-LABEL: spltMemValull
4311; P8BE-LABEL: spltMemValull
4312; P8LE-LABEL: spltMemValull
4313; P9BE: lxvdsx v2
4314; P9BE-NEXT: blr
4315; P9LE: lxvdsx v2
4316; P9LE-NEXT: blr
4317; P8BE: lxvdsx v2
4318; P8BE-NEXT: blr
4319; P8LE: lxvdsx v2
4320; P8LE-NEXT: blr
4321}
4322
4323; Function Attrs: norecurse nounwind readnone
4324define <2 x i64> @spltCnstConvftoull() {
4325entry:
4326 ret <2 x i64> <i64 4, i64 4>
4327; P9BE-LABEL: spltCnstConvftoull
4328; P9LE-LABEL: spltCnstConvftoull
4329; P8BE-LABEL: spltCnstConvftoull
4330; P8LE-LABEL: spltCnstConvftoull
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]4331; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]4332; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]4333; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]4334; P9LE: blr
4335; P8BE: lxvd2x
4336; P8BE: blr
4337; P8LE: lxvd2x
4338; P8LE: blr
4339}
4340
4341; Function Attrs: norecurse nounwind readnone
4342define <2 x i64> @fromRegsConvftoull(float %a, float %b) {
4343entry:
4344 %conv = fptoui float %a to i64
4345 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4346 %conv1 = fptoui float %b to i64
4347 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1
4348 ret <2 x i64> %vecinit2
4349; P9BE-LABEL: fromRegsConvftoull
4350; P9LE-LABEL: fromRegsConvftoull
4351; P8BE-LABEL: fromRegsConvftoull
4352; P8LE-LABEL: fromRegsConvftoull
4353; P9BE: xxmrghd
4354; P9BE: xvcvdpuxds v2
4355; P9BE-NEXT: blr
4356; P9LE: xxmrghd
4357; P9LE: xvcvdpuxds v2
4358; P9LE-NEXT: blr
4359; P8BE: xxmrghd
4360; P8BE: xvcvdpuxds v2
4361; P8BE-NEXT: blr
4362; P8LE: xxmrghd
4363; P8LE: xvcvdpuxds v2
4364; P8LE-NEXT: blr
4365}
4366
4367; Function Attrs: norecurse nounwind readnone
4368define <2 x i64> @fromDiffConstsConvftoull() {
4369entry:
4370 ret <2 x i64> <i64 24, i64 234>
4371; P9BE-LABEL: fromDiffConstsConvftoull
4372; P9LE-LABEL: fromDiffConstsConvftoull
4373; P8BE-LABEL: fromDiffConstsConvftoull
4374; P8LE-LABEL: fromDiffConstsConvftoull
Nemanja Ivanovic3c7e276d2017-07-13 18:17:10 +0000[diff] [blame^]4375; P9BE: lxvx v2
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]4376; P9BE: blr
Nemanja Ivanovic3c7e276d2017-07-13 18:17:10 +0000[diff] [blame^]4377; P9LE: lxvx v2
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]4378; P9LE: blr
4379; P8BE: lxvd2x v2
4380; P8BE: blr
4381; P8LE: lxvd2x
4382; P8LE: xxswapd v2
4383; P8LE: blr
4384}
4385
4386; Function Attrs: norecurse nounwind readonly
4387define <2 x i64> @fromDiffMemConsAConvftoull(float* nocapture readonly %ptr) {
4388entry:
4389 %0 = load float, float* %ptr, align 4
4390 %conv = fptoui float %0 to i64
4391 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4392 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 1
4393 %1 = load float, float* %arrayidx1, align 4
4394 %conv2 = fptoui float %1 to i64
4395 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
4396 ret <2 x i64> %vecinit3
4397; P9BE-LABEL: fromDiffMemConsAConvftoull
4398; P9LE-LABEL: fromDiffMemConsAConvftoull
4399; P8BE-LABEL: fromDiffMemConsAConvftoull
4400; P8LE-LABEL: fromDiffMemConsAConvftoull
4401; P9BE: lfs
4402; P9BE: lfs
4403; P9BE: xxmrghd
4404; P9BE-NEXT: xvcvdpuxds v2
4405; P9BE-NEXT: blr
4406; P9LE: lfs
4407; P9LE: lfs
4408; P9LE: xxmrghd
4409; P9LE-NEXT: xvcvdpuxds v2
4410; P9LE-NEXT: blr
4411; P8BE: lxsspx
4412; P8BE: lxsspx
4413; P8BE: xxmrghd
4414; P8BE-NEXT: xvcvdpuxds v2
4415; P8BE-NEXT: blr
4416; P8LE: lxsspx
4417; P8LE: lxsspx
4418; P8LE: xxmrghd
4419; P8LE-NEXT: xvcvdpuxds v2
4420; P8LE-NEXT: blr
4421}
4422
4423; Function Attrs: norecurse nounwind readonly
4424define <2 x i64> @fromDiffMemConsDConvftoull(float* nocapture readonly %ptr) {
4425entry:
4426 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3
4427 %0 = load float, float* %arrayidx, align 4
4428 %conv = fptoui float %0 to i64
4429 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4430 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2
4431 %1 = load float, float* %arrayidx1, align 4
4432 %conv2 = fptoui float %1 to i64
4433 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
4434 ret <2 x i64> %vecinit3
4435; P9BE-LABEL: fromDiffMemConsDConvftoull
4436; P9LE-LABEL: fromDiffMemConsDConvftoull
4437; P8BE-LABEL: fromDiffMemConsDConvftoull
4438; P8LE-LABEL: fromDiffMemConsDConvftoull
4439; P9BE: lfs
4440; P9BE: lfs
4441; P9BE: xxmrghd
4442; P9BE-NEXT: xvcvdpuxds v2
4443; P9BE-NEXT: blr
4444; P9LE: lfs
4445; P9LE: lfs
4446; P9LE: xxmrghd
4447; P9LE-NEXT: xvcvdpuxds v2
4448; P9LE-NEXT: blr
4449; P8BE: lxsspx
4450; P8BE: lxsspx
4451; P8BE: xxmrghd
4452; P8BE-NEXT: xvcvdpuxds v2
4453; P8BE-NEXT: blr
4454; P8LE: lxsspx
4455; P8LE: lxsspx
4456; P8LE: xxmrghd
4457; P8LE-NEXT: xvcvdpuxds v2
4458; P8LE-NEXT: blr
4459}
4460
4461; Function Attrs: norecurse nounwind readonly
4462define <2 x i64> @fromDiffMemVarAConvftoull(float* nocapture readonly %arr, i32 signext %elem) {
4463entry:
4464 %idxprom = sext i32 %elem to i64
4465 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom
4466 %0 = load float, float* %arrayidx, align 4
4467 %conv = fptoui float %0 to i64
4468 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4469 %add = add nsw i32 %elem, 1
4470 %idxprom1 = sext i32 %add to i64
4471 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1
4472 %1 = load float, float* %arrayidx2, align 4
4473 %conv3 = fptoui float %1 to i64
4474 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
4475 ret <2 x i64> %vecinit4
4476; P9BE-LABEL: fromDiffMemVarAConvftoull
4477; P9LE-LABEL: fromDiffMemVarAConvftoull
4478; P8BE-LABEL: fromDiffMemVarAConvftoull
4479; P8LE-LABEL: fromDiffMemVarAConvftoull
4480; P9BE: sldi
4481; P9BE: lfsux
4482; P9BE: lfs
4483; P9BE: xxmrghd
4484; P9BE-NEXT: xvcvdpuxds v2
4485; P9BE-NEXT: blr
4486; P9LE: sldi
4487; P9LE: lfsux
4488; P9LE: lfs
4489; P9LE: xxmrghd
4490; P9LE-NEXT: xvcvdpuxds v2
4491; P9LE-NEXT: blr
4492; P8BE: sldi
4493; P8BE: lfsux
4494; P8BE: lxsspx
4495; P8BE: xxmrghd
4496; P8BE-NEXT: xvcvdpuxds v2
4497; P8BE-NEXT: blr
4498; P8LE: sldi
4499; P8LE: lfsux
4500; P8LE: lxsspx
4501; P8LE: xxmrghd
4502; P8LE-NEXT: xvcvdpuxds v2
4503; P8LE-NEXT: blr
4504}
4505
4506; Function Attrs: norecurse nounwind readonly
4507define <2 x i64> @fromDiffMemVarDConvftoull(float* nocapture readonly %arr, i32 signext %elem) {
4508entry:
4509 %idxprom = sext i32 %elem to i64
4510 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom
4511 %0 = load float, float* %arrayidx, align 4
4512 %conv = fptoui float %0 to i64
4513 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4514 %sub = add nsw i32 %elem, -1
4515 %idxprom1 = sext i32 %sub to i64
4516 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1
4517 %1 = load float, float* %arrayidx2, align 4
4518 %conv3 = fptoui float %1 to i64
4519 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
4520 ret <2 x i64> %vecinit4
4521; P9BE-LABEL: fromDiffMemVarDConvftoull
4522; P9LE-LABEL: fromDiffMemVarDConvftoull
4523; P8BE-LABEL: fromDiffMemVarDConvftoull
4524; P8LE-LABEL: fromDiffMemVarDConvftoull
4525; P9BE: sldi
4526; P9BE: lfsux
4527; P9BE: lfs
4528; P9BE: xxmrghd
4529; P9BE-NEXT: xvcvdpuxds v2
4530; P9BE-NEXT: blr
4531; P9LE: sldi
4532; P9LE: lfsux
4533; P9LE: lfs
4534; P9LE: xxmrghd
4535; P9LE-NEXT: xvcvdpuxds v2
4536; P9LE-NEXT: blr
4537; P8BE: sldi
4538; P8BE: lfsux
4539; P8BE: lxsspx
4540; P8BE: xxmrghd
4541; P8BE-NEXT: xvcvdpuxds v2
4542; P8BE-NEXT: blr
4543; P8LE: sldi
4544; P8LE: lfsux
4545; P8LE: lxsspx
4546; P8LE: xxmrghd
4547; P8LE-NEXT: xvcvdpuxds v2
4548; P8LE-NEXT: blr
4549}
4550
4551; Function Attrs: norecurse nounwind readnone
4552define <2 x i64> @spltRegValConvftoull(float %val) {
4553entry:
4554 %conv = fptoui float %val to i64
4555 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
4556 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
4557 ret <2 x i64> %splat.splat
4558; P9BE-LABEL: spltRegValConvftoull
4559; P9LE-LABEL: spltRegValConvftoull
4560; P8BE-LABEL: spltRegValConvftoull
4561; P8LE-LABEL: spltRegValConvftoull
4562; P9BE: xscvdpuxds
4563; P9BE-NEXT: xxspltd v2
4564; P9BE-NEXT: blr
4565; P9LE: xscvdpuxds
4566; P9LE-NEXT: xxspltd v2
4567; P9LE-NEXT: blr
4568; P8BE: xscvdpuxds
4569; P8BE-NEXT: xxspltd v2
4570; P8BE-NEXT: blr
4571; P8LE: xscvdpuxds
4572; P8LE-NEXT: xxspltd v2
4573; P8LE-NEXT: blr
4574}
4575
4576; Function Attrs: norecurse nounwind readonly
4577define <2 x i64> @spltMemValConvftoull(float* nocapture readonly %ptr) {
4578entry:
4579 %0 = load float, float* %ptr, align 4
4580 %conv = fptoui float %0 to i64
4581 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
4582 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
4583 ret <2 x i64> %splat.splat
4584; P9BE-LABEL: spltMemValConvftoull
4585; P9LE-LABEL: spltMemValConvftoull
4586; P8BE-LABEL: spltMemValConvftoull
4587; P8LE-LABEL: spltMemValConvftoull
4588; P9BE: lfs
4589; P9BE-NEXT: xscvdpuxds
4590; P9BE-NEXT: xxspltd v2
4591; P9BE-NEXT: blr
4592; P9LE: lfs
4593; P9LE-NEXT: xscvdpuxds
4594; P9LE-NEXT: xxspltd v2
4595; P9LE-NEXT: blr
4596; P8BE: lxsspx
4597; P8BE-NEXT: xscvdpuxds
4598; P8BE-NEXT: xxspltd v2
4599; P8BE-NEXT: blr
4600; P8LE: lxsspx
4601; P8LE-NEXT: xscvdpuxds
4602; P8LE-NEXT: xxspltd v2
4603; P8LE-NEXT: blr
4604}
4605
4606; Function Attrs: norecurse nounwind readnone
4607define <2 x i64> @spltCnstConvdtoull() {
4608entry:
4609 ret <2 x i64> <i64 4, i64 4>
4610; P9BE-LABEL: spltCnstConvdtoull
4611; P9LE-LABEL: spltCnstConvdtoull
4612; P8BE-LABEL: spltCnstConvdtoull
4613; P8LE-LABEL: spltCnstConvdtoull
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]4614; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]4615; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]4616; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]4617; P9LE: blr
4618; P8BE: lxvd2x
4619; P8BE: blr
4620; P8LE: lxvd2x
4621; P8LE: blr
4622}
4623
4624; Function Attrs: norecurse nounwind readnone
4625define <2 x i64> @fromRegsConvdtoull(double %a, double %b) {
4626entry:
4627 %conv = fptoui double %a to i64
4628 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4629 %conv1 = fptoui double %b to i64
4630 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1
4631 ret <2 x i64> %vecinit2
4632; P9BE-LABEL: fromRegsConvdtoull
4633; P9LE-LABEL: fromRegsConvdtoull
4634; P8BE-LABEL: fromRegsConvdtoull
4635; P8LE-LABEL: fromRegsConvdtoull
4636; P9BE: xxmrghd
4637; P9BE-NEXT: xvcvdpuxds
4638; P9BE-NEXT: blr
4639; P9LE: xxmrghd
4640; P9LE-NEXT: xvcvdpuxds
4641; P9LE-NEXT: blr
4642; P8BE: xxmrghd
4643; P8BE-NEXT: xvcvdpuxds
4644; P8BE-NEXT: blr
4645; P8LE: xxmrghd
4646; P8LE-NEXT: xvcvdpuxds
4647; P8LE-NEXT: blr
4648}
4649
4650; Function Attrs: norecurse nounwind readnone
4651define <2 x i64> @fromDiffConstsConvdtoull() {
4652entry:
4653 ret <2 x i64> <i64 24, i64 234>
4654; P9BE-LABEL: fromDiffConstsConvdtoull
4655; P9LE-LABEL: fromDiffConstsConvdtoull
4656; P8BE-LABEL: fromDiffConstsConvdtoull
4657; P8LE-LABEL: fromDiffConstsConvdtoull
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]4658; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]4659; P9BE: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]4660; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]4661; P9LE: blr
4662; P8BE: lxvd2x
4663; P8BE: blr
4664; P8LE: lxvd2x
4665; P8LE: blr
4666}
4667
4668; Function Attrs: norecurse nounwind readonly
4669define <2 x i64> @fromDiffMemConsAConvdtoull(double* nocapture readonly %ptr) {
4670entry:
4671 %0 = bitcast double* %ptr to <2 x double>*
4672 %1 = load <2 x double>, <2 x double>* %0, align 8
4673 %2 = fptoui <2 x double> %1 to <2 x i64>
4674 ret <2 x i64> %2
4675; P9BE-LABEL: fromDiffMemConsAConvdtoull
4676; P9LE-LABEL: fromDiffMemConsAConvdtoull
4677; P8BE-LABEL: fromDiffMemConsAConvdtoull
4678; P8LE-LABEL: fromDiffMemConsAConvdtoull
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]4679; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]4680; P9BE-NEXT: xvcvdpuxds v2
4681; P9BE-NEXT: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]4682; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]4683; P9LE-NEXT: xvcvdpuxds v2
4684; P9LE-NEXT: blr
4685; P8BE: lxvd2x
4686; P8BE-NEXT: xvcvdpuxds v2
4687; P8BE-NEXT: blr
4688; P8LE: lxvd2x
4689; P8LE: xxswapd
4690; P8LE-NEXT: xvcvdpuxds v2
4691; P8LE-NEXT: blr
4692}
4693
4694; Function Attrs: norecurse nounwind readonly
4695define <2 x i64> @fromDiffMemConsDConvdtoull(double* nocapture readonly %ptr) {
4696entry:
4697 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3
4698 %0 = load double, double* %arrayidx, align 8
4699 %conv = fptoui double %0 to i64
4700 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4701 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2
4702 %1 = load double, double* %arrayidx1, align 8
4703 %conv2 = fptoui double %1 to i64
4704 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
4705 ret <2 x i64> %vecinit3
4706; P9BE-LABEL: fromDiffMemConsDConvdtoull
4707; P9LE-LABEL: fromDiffMemConsDConvdtoull
4708; P8BE-LABEL: fromDiffMemConsDConvdtoull
4709; P8LE-LABEL: fromDiffMemConsDConvdtoull
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]4710; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]4711; P9BE-NEXT: xxswapd
4712; P9BE-NEXT: xvcvdpuxds v2
4713; P9BE-NEXT: blr
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]4714; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]4715; P9LE-NEXT: xxswapd
4716; P9LE-NEXT: xvcvdpuxds v2
4717; P9LE-NEXT: blr
4718; P8BE: lxvd2x
4719; P8BE-NEXT: xxswapd
4720; P8BE-NEXT: xvcvdpuxds v2
4721; P8BE-NEXT: blr
4722; P8LE: lxvd2x
4723; P8LE-NEXT: xvcvdpuxds v2
4724; P8LE-NEXT: blr
4725}
4726
4727; Function Attrs: norecurse nounwind readonly
4728define <2 x i64> @fromDiffMemVarAConvdtoull(double* nocapture readonly %arr, i32 signext %elem) {
4729entry:
4730 %idxprom = sext i32 %elem to i64
4731 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom
4732 %0 = load double, double* %arrayidx, align 8
4733 %conv = fptoui double %0 to i64
4734 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4735 %add = add nsw i32 %elem, 1
4736 %idxprom1 = sext i32 %add to i64
4737 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1
4738 %1 = load double, double* %arrayidx2, align 8
4739 %conv3 = fptoui double %1 to i64
4740 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
4741 ret <2 x i64> %vecinit4
4742; P9BE-LABEL: fromDiffMemVarAConvdtoull
4743; P9LE-LABEL: fromDiffMemVarAConvdtoull
4744; P8BE-LABEL: fromDiffMemVarAConvdtoull
4745; P8LE-LABEL: fromDiffMemVarAConvdtoull
4746; P9BE: sldi
4747; P9BE: lxvx
4748; P9BE-NEXT: xvcvdpuxds v2
4749; P9BE-NEXT: blr
4750; P9LE: sldi
4751; P9LE: lxvx
4752; P9LE-NEXT: xvcvdpuxds v2
4753; P9LE-NEXT: blr
4754; P8BE: sldi
4755; P8BE: lxvd2x
4756; P8BE-NEXT: xvcvdpuxds v2
4757; P8BE-NEXT: blr
4758; P8LE: sldi
4759; P8LE: lxvd2x
4760; P8LE-NEXT: xxswapd
4761; P8LE-NEXT: xvcvdpuxds v2
4762; P8LE-NEXT: blr
4763}
4764
4765; Function Attrs: norecurse nounwind readonly
4766define <2 x i64> @fromDiffMemVarDConvdtoull(double* nocapture readonly %arr, i32 signext %elem) {
4767entry:
4768 %idxprom = sext i32 %elem to i64
4769 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom
4770 %0 = load double, double* %arrayidx, align 8
4771 %conv = fptoui double %0 to i64
4772 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4773 %sub = add nsw i32 %elem, -1
4774 %idxprom1 = sext i32 %sub to i64
4775 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1
4776 %1 = load double, double* %arrayidx2, align 8
4777 %conv3 = fptoui double %1 to i64
4778 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
4779 ret <2 x i64> %vecinit4
4780; P9BE-LABEL: fromDiffMemVarDConvdtoull
4781; P9LE-LABEL: fromDiffMemVarDConvdtoull
4782; P8BE-LABEL: fromDiffMemVarDConvdtoull
4783; P8LE-LABEL: fromDiffMemVarDConvdtoull
4784; P9BE: sldi
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]4785; P9BE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]4786; P9BE-NEXT: xxswapd
4787; P9BE-NEXT: xvcvdpuxds v2
4788; P9BE-NEXT: blr
4789; P9LE: sldi
Zaara Syeda93297832017-05-24 17:50:37 +0000[diff] [blame]4790; P9LE: lxv
Nemanja Ivanovic15748f42016-12-06 11:47:14 +0000[diff] [blame]4791; P9LE-NEXT: xxswapd
4792; P9LE-NEXT: xvcvdpuxds v2
4793; P9LE-NEXT: blr
4794; P8BE: sldi
4795; P8BE: lxvd2x
4796; P8BE-NEXT: xxswapd
4797; P8BE-NEXT: xvcvdpuxds v2
4798; P8BE-NEXT: blr
4799; P8LE: sldi
4800; P8LE: lxvd2x
4801; P8LE-NEXT: xvcvdpuxds v2
4802; P8LE-NEXT: blr
4803}
4804
4805; Function Attrs: norecurse nounwind readnone
4806define <2 x i64> @spltRegValConvdtoull(double %val) {
4807entry:
4808 %conv = fptoui double %val to i64
4809 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
4810 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
4811 ret <2 x i64> %splat.splat
4812; P9BE-LABEL: spltRegValConvdtoull
4813; P9LE-LABEL: spltRegValConvdtoull
4814; P8BE-LABEL: spltRegValConvdtoull
4815; P8LE-LABEL: spltRegValConvdtoull
4816; P9BE: xscvdpuxds
4817; P9BE-NEXT: xxspltd v2
4818; P9BE-NEXT: blr
4819; P9LE: xscvdpuxds
4820; P9LE-NEXT: xxspltd v2
4821; P9LE-NEXT: blr
4822; P8BE: xscvdpuxds
4823; P8BE-NEXT: xxspltd v2
4824; P8BE-NEXT: blr
4825; P8LE: xscvdpuxds
4826; P8LE-NEXT: xxspltd v2
4827; P8LE-NEXT: blr
4828}
4829
4830; Function Attrs: norecurse nounwind readonly
4831define <2 x i64> @spltMemValConvdtoull(double* nocapture readonly %ptr) {
4832entry:
4833 %0 = load double, double* %ptr, align 8
4834 %conv = fptoui double %0 to i64
4835 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
4836 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
4837 ret <2 x i64> %splat.splat
4838; P9BE-LABEL: spltMemValConvdtoull
4839; P9LE-LABEL: spltMemValConvdtoull
4840; P8BE-LABEL: spltMemValConvdtoull
4841; P8LE-LABEL: spltMemValConvdtoull
4842; P9BE: lxvdsx
4843; P9BE-NEXT: xvcvdpuxds
4844; P9BE-NEXT: blr
4845; P9LE: lxvdsx
4846; P9LE-NEXT: xvcvdpuxds
4847; P9LE-NEXT: blr
4848; P8BE: lxvdsx
4849; P8BE-NEXT: xvcvdpuxds
4850; P8BE-NEXT: blr
4851; P8LE: lxvdsx
4852; P8LE-NEXT: xvcvdpuxds
4853; P8LE-NEXT: blr
4854}