| Vincent Lejeune | 68b6b6d | 2013-03-05 18:41:32 +0000 | [diff] [blame] | 1 | //===-- R600MachineScheduler.h - R600 Scheduler Interface -*- C++ -*-------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | /// \file |
| 11 | /// \brief R600 Machine Scheduler interface |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
| 15 | #ifndef R600MACHINESCHEDULER_H_ |
| 16 | #define R600MACHINESCHEDULER_H_ |
| 17 | |
| 18 | #include "R600InstrInfo.h" |
| 19 | #include "llvm/CodeGen/MachineScheduler.h" |
| 20 | #include "llvm/Support/Debug.h" |
| 21 | #include "llvm/ADT/PriorityQueue.h" |
| 22 | |
| 23 | using namespace llvm; |
| 24 | |
| 25 | namespace llvm { |
| 26 | |
| Vincent Lejeune | 68b6b6d | 2013-03-05 18:41:32 +0000 | [diff] [blame] | 27 | class R600SchedStrategy : public MachineSchedStrategy { |
| 28 | |
| 29 | const ScheduleDAGMI *DAG; |
| 30 | const R600InstrInfo *TII; |
| 31 | const R600RegisterInfo *TRI; |
| 32 | MachineRegisterInfo *MRI; |
| 33 | |
| Vincent Lejeune | 68b6b6d | 2013-03-05 18:41:32 +0000 | [diff] [blame] | 34 | enum InstKind { |
| 35 | IDAlu, |
| 36 | IDFetch, |
| 37 | IDOther, |
| 38 | IDLast |
| 39 | }; |
| 40 | |
| 41 | enum AluKind { |
| 42 | AluAny, |
| 43 | AluT_X, |
| 44 | AluT_Y, |
| 45 | AluT_Z, |
| 46 | AluT_W, |
| 47 | AluT_XYZW, |
| Vincent Lejeune | 3d5118c | 2013-05-17 16:50:56 +0000 | [diff] [blame^] | 48 | AluPredX, |
| Vincent Lejeune | 68b6b6d | 2013-03-05 18:41:32 +0000 | [diff] [blame] | 49 | AluDiscarded, // LLVM Instructions that are going to be eliminated |
| 50 | AluLast |
| 51 | }; |
| 52 | |
| Vincent Lejeune | 4c81d4d | 2013-05-17 16:50:44 +0000 | [diff] [blame] | 53 | std::vector<SUnit *> Available[IDLast], Pending[IDLast]; |
| 54 | std::vector<SUnit *> AvailableAlus[AluLast]; |
| Vincent Lejeune | 68b6b6d | 2013-03-05 18:41:32 +0000 | [diff] [blame] | 55 | |
| 56 | InstKind CurInstKind; |
| 57 | int CurEmitted; |
| 58 | InstKind NextInstKind; |
| 59 | |
| 60 | int InstKindLimit[IDLast]; |
| 61 | |
| 62 | int OccupedSlotsMask; |
| 63 | |
| 64 | public: |
| 65 | R600SchedStrategy() : |
| 66 | DAG(0), TII(0), TRI(0), MRI(0) { |
| Vincent Lejeune | 68b6b6d | 2013-03-05 18:41:32 +0000 | [diff] [blame] | 67 | } |
| 68 | |
| 69 | virtual ~R600SchedStrategy() { |
| Vincent Lejeune | 68b6b6d | 2013-03-05 18:41:32 +0000 | [diff] [blame] | 70 | } |
| 71 | |
| 72 | virtual void initialize(ScheduleDAGMI *dag); |
| 73 | virtual SUnit *pickNode(bool &IsTopNode); |
| 74 | virtual void schedNode(SUnit *SU, bool IsTopNode); |
| 75 | virtual void releaseTopNode(SUnit *SU); |
| 76 | virtual void releaseBottomNode(SUnit *SU); |
| 77 | |
| 78 | private: |
| Vincent Lejeune | 0a22bc4 | 2013-03-14 15:50:45 +0000 | [diff] [blame] | 79 | std::vector<MachineInstr *> InstructionsGroupCandidate; |
| Vincent Lejeune | 68b6b6d | 2013-03-05 18:41:32 +0000 | [diff] [blame] | 80 | |
| 81 | int getInstKind(SUnit *SU); |
| 82 | bool regBelongsToClass(unsigned Reg, const TargetRegisterClass *RC) const; |
| 83 | AluKind getAluKind(SUnit *SU) const; |
| 84 | void LoadAlu(); |
| 85 | bool isAvailablesAluEmpty() const; |
| 86 | SUnit *AttemptFillSlot (unsigned Slot); |
| 87 | void PrepareNextSlot(); |
| Vincent Lejeune | 4c81d4d | 2013-05-17 16:50:44 +0000 | [diff] [blame] | 88 | SUnit *PopInst(std::vector<SUnit*> &Q); |
| Vincent Lejeune | 68b6b6d | 2013-03-05 18:41:32 +0000 | [diff] [blame] | 89 | |
| 90 | void AssignSlot(MachineInstr *MI, unsigned Slot); |
| 91 | SUnit* pickAlu(); |
| 92 | SUnit* pickOther(int QID); |
| Vincent Lejeune | 4c81d4d | 2013-05-17 16:50:44 +0000 | [diff] [blame] | 93 | void MoveUnits(std::vector<SUnit *> &QSrc, std::vector<SUnit *> &QDst); |
| Vincent Lejeune | 68b6b6d | 2013-03-05 18:41:32 +0000 | [diff] [blame] | 94 | }; |
| 95 | |
| 96 | } // namespace llvm |
| 97 | |
| 98 | #endif /* R600MACHINESCHEDULER_H_ */ |