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gerrit-public.fairphone.software / toolchain / llvm-project / 3eb45a03afe8cb667864adb350003f08f15f680d / . / llvm / test / CodeGen / ARM / atomic-64bit.ll
blob: 4ac5e5d323331c043d90bce9eb921244ea80d614 [file] [log] [blame]
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]1; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s
2
3define i64 @test1(i64* %ptr, i64 %val) {
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]4; CHECK: test1:
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]5; CHECK: dmb ish
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]6; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
7; CHECK: adds [[REG3:(r[0-9]?[02468])]], [[REG1]]
8; CHECK: adc [[REG4:(r[0-9]?[13579])]], [[REG2]]
9; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]10; CHECK: cmp
11; CHECK: bne
12; CHECK: dmb ish
13 %r = atomicrmw add i64* %ptr, i64 %val seq_cst
14 ret i64 %r
15}
16
17define i64 @test2(i64* %ptr, i64 %val) {
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]18; CHECK: test2:
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]19; CHECK: dmb ish
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]20; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
21; CHECK: subs [[REG3:(r[0-9]?[02468])]], [[REG1]]
22; CHECK: sbc [[REG4:(r[0-9]?[13579])]], [[REG2]]
23; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]24; CHECK: cmp
25; CHECK: bne
26; CHECK: dmb ish
27 %r = atomicrmw sub i64* %ptr, i64 %val seq_cst
28 ret i64 %r
29}
30
31define i64 @test3(i64* %ptr, i64 %val) {
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]32; CHECK: test3:
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]33; CHECK: dmb ish
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]34; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
35; CHECK: and [[REG3:(r[0-9]?[02468])]], [[REG1]]
36; CHECK: and [[REG4:(r[0-9]?[13579])]], [[REG2]]
37; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]38; CHECK: cmp
39; CHECK: bne
40; CHECK: dmb ish
41 %r = atomicrmw and i64* %ptr, i64 %val seq_cst
42 ret i64 %r
43}
44
45define i64 @test4(i64* %ptr, i64 %val) {
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]46; CHECK: test4:
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]47; CHECK: dmb ish
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]48; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
49; CHECK: orr [[REG3:(r[0-9]?[02468])]], [[REG1]]
50; CHECK: orr [[REG4:(r[0-9]?[13579])]], [[REG2]]
51; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]52; CHECK: cmp
53; CHECK: bne
54; CHECK: dmb ish
55 %r = atomicrmw or i64* %ptr, i64 %val seq_cst
56 ret i64 %r
57}
58
59define i64 @test5(i64* %ptr, i64 %val) {
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]60; CHECK: test5:
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]61; CHECK: dmb ish
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]62; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
63; CHECK: eor [[REG3:(r[0-9]?[02468])]], [[REG1]]
64; CHECK: eor [[REG4:(r[0-9]?[13579])]], [[REG2]]
65; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]66; CHECK: cmp
67; CHECK: bne
68; CHECK: dmb ish
69 %r = atomicrmw xor i64* %ptr, i64 %val seq_cst
70 ret i64 %r
71}
72
73define i64 @test6(i64* %ptr, i64 %val) {
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]74; CHECK: test6:
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]75; CHECK: dmb ish
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]76; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
77; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]78; CHECK: cmp
79; CHECK: bne
80; CHECK: dmb ish
81 %r = atomicrmw xchg i64* %ptr, i64 %val seq_cst
82 ret i64 %r
Eli Friedman2c7bb522011-08-31 00:41:05 +0000[diff] [blame]83}
Eli Friedman1ccecbb2011-08-31 17:52:22 +0000[diff] [blame]84
85define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) {
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]86; CHECK: test7:
Eli Friedman1ccecbb2011-08-31 17:52:22 +0000[diff] [blame]87; CHECK: dmb ish
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]88; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
89; CHECK: cmp [[REG1]]
90; CHECK: cmpeq [[REG2]]
Eli Friedman1ccecbb2011-08-31 17:52:22 +0000[diff] [blame]91; CHECK: bne
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]92; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
Eli Friedman1ccecbb2011-08-31 17:52:22 +0000[diff] [blame]93; CHECK: cmp
94; CHECK: bne
95; CHECK: dmb ish
96 %r = cmpxchg i64* %ptr, i64 %val1, i64 %val2 seq_cst
97 ret i64 %r
98}
Eli Friedman7c3bded2011-08-31 18:26:09 +0000[diff] [blame]99
100; Compiles down to cmpxchg
101; FIXME: Should compile to a single ldrexd
102define i64 @test8(i64* %ptr) {
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]103; CHECK: test8:
104; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
105; CHECK: cmp [[REG1]]
106; CHECK: cmpeq [[REG2]]
Eli Friedman7c3bded2011-08-31 18:26:09 +0000[diff] [blame]107; CHECK: bne
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]108; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
Eli Friedman7c3bded2011-08-31 18:26:09 +0000[diff] [blame]109; CHECK: cmp
110; CHECK: bne
111; CHECK: dmb ish
112 %r = load atomic i64* %ptr seq_cst, align 8
113 ret i64 %r
114}
115
116; Compiles down to atomicrmw xchg; there really isn't any more efficient
117; way to write it.
118define void @test9(i64* %ptr, i64 %val) {
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]119; CHECK: test9:
Eli Friedman7c3bded2011-08-31 18:26:09 +0000[diff] [blame]120; CHECK: dmb ish
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]121; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
122; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
Eli Friedman7c3bded2011-08-31 18:26:09 +0000[diff] [blame]123; CHECK: cmp
124; CHECK: bne
125; CHECK: dmb ish
126 store atomic i64 %val, i64* %ptr seq_cst, align 8
127 ret void
128}
Silviu Baranga93aefa52012-11-29 14:41:25 +0000[diff] [blame]129
130define i64 @test10(i64* %ptr, i64 %val) {
131; CHECK: test10:
132; CHECK: dmb ish
133; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
134; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
135; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
Silviu Baranga3eb45a02013-01-25 10:39:49 +0000[diff] [blame^]136; CHECK: blt
Silviu Baranga93aefa52012-11-29 14:41:25 +0000[diff] [blame]137; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
138; CHECK: cmp
139; CHECK: bne
140; CHECK: dmb ish
141 %r = atomicrmw min i64* %ptr, i64 %val seq_cst
142 ret i64 %r
143}
144
145define i64 @test11(i64* %ptr, i64 %val) {
146; CHECK: test11:
147; CHECK: dmb ish
148; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
149; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
150; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
Silviu Baranga3eb45a02013-01-25 10:39:49 +0000[diff] [blame^]151; CHECK: blo
Silviu Baranga93aefa52012-11-29 14:41:25 +0000[diff] [blame]152; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
153; CHECK: cmp
154; CHECK: bne
155; CHECK: dmb ish
156 %r = atomicrmw umin i64* %ptr, i64 %val seq_cst
157 ret i64 %r
158}
159
160define i64 @test12(i64* %ptr, i64 %val) {
161; CHECK: test12:
162; CHECK: dmb ish
163; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
164; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
165; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
166; CHECK: bge
167; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
168; CHECK: cmp
169; CHECK: bne
170; CHECK: dmb ish
171 %r = atomicrmw max i64* %ptr, i64 %val seq_cst
172 ret i64 %r
173}
174
175define i64 @test13(i64* %ptr, i64 %val) {
176; CHECK: test13:
177; CHECK: dmb ish
178; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
179; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
180; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
181; CHECK: bhs
182; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
183; CHECK: cmp
184; CHECK: bne
185; CHECK: dmb ish
186 %r = atomicrmw umax i64* %ptr, i64 %val seq_cst
187 ret i64 %r
188}
189