Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / 3f8d8f5f4395f062dcdbf7d41debe92c72713615 / . / llvm / test / CodeGen / X86 / build-vector-512.ll
blob: 21737cca93a10bcfa99b783b4b549a456ca710db [file] [log] [blame]
Simon Pilgrim3f8d8f52017-05-05 15:36:31 +0000[diff] [blame^]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=AVX-32 --check-prefix=AVX512F-32
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=AVX-64 --check-prefix=AVX512F-64
4; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefix=AVX-32 --check-prefix=AVX512BW-32
5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefix=AVX-64 --check-prefix=AVX512BW-64
6
7define <8 x double> @test_buildvector_v8f64(double %a0, double %a1, double %a2, double %a3, double %a4, double %a5, double %a6, double %a7) {
8; AVX-32-LABEL: test_buildvector_v8f64:
9; AVX-32: # BB#0:
10; AVX-32-NEXT: vmovups {{[0-9]+}}(%esp), %zmm0
11; AVX-32-NEXT: retl
12;
13; AVX-64-LABEL: test_buildvector_v8f64:
14; AVX-64: # BB#0:
15; AVX-64-NEXT: vunpcklpd {{.*#+}} xmm6 = xmm6[0],xmm7[0]
16; AVX-64-NEXT: vunpcklpd {{.*#+}} xmm4 = xmm4[0],xmm5[0]
17; AVX-64-NEXT: vinsertf128 $1, %xmm6, %ymm4, %ymm4
18; AVX-64-NEXT: vunpcklpd {{.*#+}} xmm2 = xmm2[0],xmm3[0]
19; AVX-64-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
20; AVX-64-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
21; AVX-64-NEXT: vinsertf64x4 $1, %ymm4, %zmm0, %zmm0
22; AVX-64-NEXT: retq
23 %ins0 = insertelement <8 x double> undef, double %a0, i32 0
24 %ins1 = insertelement <8 x double> %ins0, double %a1, i32 1
25 %ins2 = insertelement <8 x double> %ins1, double %a2, i32 2
26 %ins3 = insertelement <8 x double> %ins2, double %a3, i32 3
27 %ins4 = insertelement <8 x double> %ins3, double %a4, i32 4
28 %ins5 = insertelement <8 x double> %ins4, double %a5, i32 5
29 %ins6 = insertelement <8 x double> %ins5, double %a6, i32 6
30 %ins7 = insertelement <8 x double> %ins6, double %a7, i32 7
31 ret <8 x double> %ins7
32}
33
34define <16 x float> @test_buildvector_v16f32(float %a0, float %a1, float %a2, float %a3, float %a4, float %a5, float %a6, float %a7, float %a8, float %a9, float %a10, float %a11, float %a12, float %a13, float %a14, float %a15) {
35; AVX-32-LABEL: test_buildvector_v16f32:
36; AVX-32: # BB#0:
37; AVX-32-NEXT: vmovups {{[0-9]+}}(%esp), %zmm0
38; AVX-32-NEXT: retl
39;
40; AVX-64-LABEL: test_buildvector_v16f32:
41; AVX-64: # BB#0:
42; AVX-64-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[2,3]
43; AVX-64-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0,1],xmm6[0],xmm4[3]
44; AVX-64-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0,1,2],xmm7[0]
45; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
46; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]
47; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]
48; AVX-64-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
49; AVX-64-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
50; AVX-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3]
51; AVX-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3]
52; AVX-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],mem[0]
53; AVX-64-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
54; AVX-64-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3]
55; AVX-64-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3]
56; AVX-64-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0]
57; AVX-64-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
58; AVX-64-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
59; AVX-64-NEXT: retq
60 %ins0 = insertelement <16 x float> undef, float %a0, i32 0
61 %ins1 = insertelement <16 x float> %ins0, float %a1, i32 1
62 %ins2 = insertelement <16 x float> %ins1, float %a2, i32 2
63 %ins3 = insertelement <16 x float> %ins2, float %a3, i32 3
64 %ins4 = insertelement <16 x float> %ins3, float %a4, i32 4
65 %ins5 = insertelement <16 x float> %ins4, float %a5, i32 5
66 %ins6 = insertelement <16 x float> %ins5, float %a6, i32 6
67 %ins7 = insertelement <16 x float> %ins6, float %a7, i32 7
68 %ins8 = insertelement <16 x float> %ins7, float %a8, i32 8
69 %ins9 = insertelement <16 x float> %ins8, float %a9, i32 9
70 %ins10 = insertelement <16 x float> %ins9, float %a10, i32 10
71 %ins11 = insertelement <16 x float> %ins10, float %a11, i32 11
72 %ins12 = insertelement <16 x float> %ins11, float %a12, i32 12
73 %ins13 = insertelement <16 x float> %ins12, float %a13, i32 13
74 %ins14 = insertelement <16 x float> %ins13, float %a14, i32 14
75 %ins15 = insertelement <16 x float> %ins14, float %a15, i32 15
76 ret <16 x float> %ins15
77}
78
79define <8 x i64> @test_buildvector_v8i64(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5, i64 %a6, i64 %a7) {
80; AVX-32-LABEL: test_buildvector_v8i64:
81; AVX-32: # BB#0:
82; AVX-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
83; AVX-32-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm0, %xmm0
84; AVX-32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0
85; AVX-32-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0
86; AVX-32-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
87; AVX-32-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm1, %xmm1
88; AVX-32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm1, %xmm1
89; AVX-32-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm1, %xmm1
90; AVX-32-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
91; AVX-32-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
92; AVX-32-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm1, %xmm1
93; AVX-32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm1, %xmm1
94; AVX-32-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm1, %xmm1
95; AVX-32-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero
96; AVX-32-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm2, %xmm2
97; AVX-32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm2, %xmm2
98; AVX-32-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm2, %xmm2
99; AVX-32-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
100; AVX-32-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
101; AVX-32-NEXT: retl
102;
103; AVX-64-LABEL: test_buildvector_v8i64:
104; AVX-64: # BB#0:
105; AVX-64-NEXT: vmovq %rcx, %xmm0
106; AVX-64-NEXT: vmovq %rdx, %xmm1
107; AVX-64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
108; AVX-64-NEXT: vmovq %rsi, %xmm1
109; AVX-64-NEXT: vmovq %rdi, %xmm2
110; AVX-64-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
111; AVX-64-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
112; AVX-64-NEXT: vmovq %r9, %xmm1
113; AVX-64-NEXT: vmovq %r8, %xmm2
114; AVX-64-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
115; AVX-64-NEXT: vinserti128 $1, {{[0-9]+}}(%rsp), %ymm1, %ymm1
116; AVX-64-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
117; AVX-64-NEXT: retq
118 %ins0 = insertelement <8 x i64> undef, i64 %a0, i32 0
119 %ins1 = insertelement <8 x i64> %ins0, i64 %a1, i32 1
120 %ins2 = insertelement <8 x i64> %ins1, i64 %a2, i32 2
121 %ins3 = insertelement <8 x i64> %ins2, i64 %a3, i32 3
122 %ins4 = insertelement <8 x i64> %ins3, i64 %a4, i32 4
123 %ins5 = insertelement <8 x i64> %ins4, i64 %a5, i32 5
124 %ins6 = insertelement <8 x i64> %ins5, i64 %a6, i32 6
125 %ins7 = insertelement <8 x i64> %ins6, i64 %a7, i32 7
126 ret <8 x i64> %ins7
127}
128
129define <16 x i32> @test_buildvector_v16i32(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8, i32 %a9, i32 %a10, i32 %a11, i32 %a12, i32 %a13, i32 %a14, i32 %a15) {
130; AVX-32-LABEL: test_buildvector_v16i32:
131; AVX-32: # BB#0:
132; AVX-32-NEXT: vmovups {{[0-9]+}}(%esp), %zmm0
133; AVX-32-NEXT: retl
134;
135; AVX-64-LABEL: test_buildvector_v16i32:
136; AVX-64: # BB#0:
137; AVX-64-NEXT: vmovd %edi, %xmm0
138; AVX-64-NEXT: vpinsrd $1, %esi, %xmm0, %xmm0
139; AVX-64-NEXT: vpinsrd $2, %edx, %xmm0, %xmm0
140; AVX-64-NEXT: vpinsrd $3, %ecx, %xmm0, %xmm0
141; AVX-64-NEXT: vmovd %r8d, %xmm1
142; AVX-64-NEXT: vpinsrd $1, %r9d, %xmm1, %xmm1
143; AVX-64-NEXT: vpinsrd $2, {{[0-9]+}}(%rsp), %xmm1, %xmm1
144; AVX-64-NEXT: vpinsrd $3, {{[0-9]+}}(%rsp), %xmm1, %xmm1
145; AVX-64-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
146; AVX-64-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
147; AVX-64-NEXT: vpinsrd $1, {{[0-9]+}}(%rsp), %xmm1, %xmm1
148; AVX-64-NEXT: vpinsrd $2, {{[0-9]+}}(%rsp), %xmm1, %xmm1
149; AVX-64-NEXT: vpinsrd $3, {{[0-9]+}}(%rsp), %xmm1, %xmm1
150; AVX-64-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero
151; AVX-64-NEXT: vpinsrd $1, {{[0-9]+}}(%rsp), %xmm2, %xmm2
152; AVX-64-NEXT: vpinsrd $2, {{[0-9]+}}(%rsp), %xmm2, %xmm2
153; AVX-64-NEXT: vpinsrd $3, {{[0-9]+}}(%rsp), %xmm2, %xmm2
154; AVX-64-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
155; AVX-64-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
156; AVX-64-NEXT: retq
157 %ins0 = insertelement <16 x i32> undef, i32 %a0, i32 0
158 %ins1 = insertelement <16 x i32> %ins0, i32 %a1, i32 1
159 %ins2 = insertelement <16 x i32> %ins1, i32 %a2, i32 2
160 %ins3 = insertelement <16 x i32> %ins2, i32 %a3, i32 3
161 %ins4 = insertelement <16 x i32> %ins3, i32 %a4, i32 4
162 %ins5 = insertelement <16 x i32> %ins4, i32 %a5, i32 5
163 %ins6 = insertelement <16 x i32> %ins5, i32 %a6, i32 6
164 %ins7 = insertelement <16 x i32> %ins6, i32 %a7, i32 7
165 %ins8 = insertelement <16 x i32> %ins7, i32 %a8, i32 8
166 %ins9 = insertelement <16 x i32> %ins8, i32 %a9, i32 9
167 %ins10 = insertelement <16 x i32> %ins9, i32 %a10, i32 10
168 %ins11 = insertelement <16 x i32> %ins10, i32 %a11, i32 11
169 %ins12 = insertelement <16 x i32> %ins11, i32 %a12, i32 12
170 %ins13 = insertelement <16 x i32> %ins12, i32 %a13, i32 13
171 %ins14 = insertelement <16 x i32> %ins13, i32 %a14, i32 14
172 %ins15 = insertelement <16 x i32> %ins14, i32 %a15, i32 15
173 ret <16 x i32> %ins15
174}
175
176define <32 x i16> @test_buildvector_v32i16(i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7, i16 %a8, i16 %a9, i16 %a10, i16 %a11, i16 %a12, i16 %a13, i16 %a14, i16 %a15, i16 %a16, i16 %a17, i16 %a18, i16 %a19, i16 %a20, i16 %a21, i16 %a22, i16 %a23, i16 %a24, i16 %a25, i16 %a26, i16 %a27, i16 %a28, i16 %a29, i16 %a30, i16 %a31) {
177; AVX512F-32-LABEL: test_buildvector_v32i16:
178; AVX512F-32: # BB#0:
179; AVX512F-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
180; AVX512F-32-NEXT: vpinsrw $1, {{[0-9]+}}(%esp), %xmm0, %xmm0
181; AVX512F-32-NEXT: vpinsrw $2, {{[0-9]+}}(%esp), %xmm0, %xmm0
182; AVX512F-32-NEXT: vpinsrw $3, {{[0-9]+}}(%esp), %xmm0, %xmm0
183; AVX512F-32-NEXT: vpinsrw $4, {{[0-9]+}}(%esp), %xmm0, %xmm0
184; AVX512F-32-NEXT: vpinsrw $5, {{[0-9]+}}(%esp), %xmm0, %xmm0
185; AVX512F-32-NEXT: vpinsrw $6, {{[0-9]+}}(%esp), %xmm0, %xmm0
186; AVX512F-32-NEXT: vpinsrw $7, {{[0-9]+}}(%esp), %xmm0, %xmm0
187; AVX512F-32-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
188; AVX512F-32-NEXT: vpinsrw $1, {{[0-9]+}}(%esp), %xmm1, %xmm1
189; AVX512F-32-NEXT: vpinsrw $2, {{[0-9]+}}(%esp), %xmm1, %xmm1
190; AVX512F-32-NEXT: vpinsrw $3, {{[0-9]+}}(%esp), %xmm1, %xmm1
191; AVX512F-32-NEXT: vpinsrw $4, {{[0-9]+}}(%esp), %xmm1, %xmm1
192; AVX512F-32-NEXT: vpinsrw $5, {{[0-9]+}}(%esp), %xmm1, %xmm1
193; AVX512F-32-NEXT: vpinsrw $6, {{[0-9]+}}(%esp), %xmm1, %xmm1
194; AVX512F-32-NEXT: vpinsrw $7, {{[0-9]+}}(%esp), %xmm1, %xmm1
195; AVX512F-32-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
196; AVX512F-32-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
197; AVX512F-32-NEXT: vpinsrw $1, {{[0-9]+}}(%esp), %xmm1, %xmm1
198; AVX512F-32-NEXT: vpinsrw $2, {{[0-9]+}}(%esp), %xmm1, %xmm1
199; AVX512F-32-NEXT: vpinsrw $3, {{[0-9]+}}(%esp), %xmm1, %xmm1
200; AVX512F-32-NEXT: vpinsrw $4, {{[0-9]+}}(%esp), %xmm1, %xmm1
201; AVX512F-32-NEXT: vpinsrw $5, {{[0-9]+}}(%esp), %xmm1, %xmm1
202; AVX512F-32-NEXT: vpinsrw $6, {{[0-9]+}}(%esp), %xmm1, %xmm1
203; AVX512F-32-NEXT: vpinsrw $7, {{[0-9]+}}(%esp), %xmm1, %xmm1
204; AVX512F-32-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero
205; AVX512F-32-NEXT: vpinsrw $1, {{[0-9]+}}(%esp), %xmm2, %xmm2
206; AVX512F-32-NEXT: vpinsrw $2, {{[0-9]+}}(%esp), %xmm2, %xmm2
207; AVX512F-32-NEXT: vpinsrw $3, {{[0-9]+}}(%esp), %xmm2, %xmm2
208; AVX512F-32-NEXT: vpinsrw $4, {{[0-9]+}}(%esp), %xmm2, %xmm2
209; AVX512F-32-NEXT: vpinsrw $5, {{[0-9]+}}(%esp), %xmm2, %xmm2
210; AVX512F-32-NEXT: vpinsrw $6, {{[0-9]+}}(%esp), %xmm2, %xmm2
211; AVX512F-32-NEXT: vpinsrw $7, {{[0-9]+}}(%esp), %xmm2, %xmm2
212; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
213; AVX512F-32-NEXT: retl
214;
215; AVX512F-64-LABEL: test_buildvector_v32i16:
216; AVX512F-64: # BB#0:
217; AVX512F-64-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
218; AVX512F-64-NEXT: vpinsrw $1, {{[0-9]+}}(%rsp), %xmm0, %xmm0
219; AVX512F-64-NEXT: vpinsrw $2, {{[0-9]+}}(%rsp), %xmm0, %xmm0
220; AVX512F-64-NEXT: vpinsrw $3, {{[0-9]+}}(%rsp), %xmm0, %xmm0
221; AVX512F-64-NEXT: vpinsrw $4, {{[0-9]+}}(%rsp), %xmm0, %xmm0
222; AVX512F-64-NEXT: vpinsrw $5, {{[0-9]+}}(%rsp), %xmm0, %xmm0
223; AVX512F-64-NEXT: vpinsrw $6, {{[0-9]+}}(%rsp), %xmm0, %xmm0
224; AVX512F-64-NEXT: vpinsrw $7, {{[0-9]+}}(%rsp), %xmm0, %xmm0
225; AVX512F-64-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
226; AVX512F-64-NEXT: vpinsrw $1, {{[0-9]+}}(%rsp), %xmm1, %xmm1
227; AVX512F-64-NEXT: vpinsrw $2, {{[0-9]+}}(%rsp), %xmm1, %xmm1
228; AVX512F-64-NEXT: vpinsrw $3, {{[0-9]+}}(%rsp), %xmm1, %xmm1
229; AVX512F-64-NEXT: vpinsrw $4, {{[0-9]+}}(%rsp), %xmm1, %xmm1
230; AVX512F-64-NEXT: vpinsrw $5, {{[0-9]+}}(%rsp), %xmm1, %xmm1
231; AVX512F-64-NEXT: vpinsrw $6, {{[0-9]+}}(%rsp), %xmm1, %xmm1
232; AVX512F-64-NEXT: vpinsrw $7, {{[0-9]+}}(%rsp), %xmm1, %xmm1
233; AVX512F-64-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm1
234; AVX512F-64-NEXT: vmovd %edi, %xmm0
235; AVX512F-64-NEXT: vpinsrw $1, %esi, %xmm0, %xmm0
236; AVX512F-64-NEXT: vpinsrw $2, %edx, %xmm0, %xmm0
237; AVX512F-64-NEXT: vpinsrw $3, %ecx, %xmm0, %xmm0
238; AVX512F-64-NEXT: vpinsrw $4, %r8d, %xmm0, %xmm0
239; AVX512F-64-NEXT: vpinsrw $5, %r9d, %xmm0, %xmm0
240; AVX512F-64-NEXT: vpinsrw $6, {{[0-9]+}}(%rsp), %xmm0, %xmm0
241; AVX512F-64-NEXT: vpinsrw $7, {{[0-9]+}}(%rsp), %xmm0, %xmm0
242; AVX512F-64-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero
243; AVX512F-64-NEXT: vpinsrw $1, {{[0-9]+}}(%rsp), %xmm2, %xmm2
244; AVX512F-64-NEXT: vpinsrw $2, {{[0-9]+}}(%rsp), %xmm2, %xmm2
245; AVX512F-64-NEXT: vpinsrw $3, {{[0-9]+}}(%rsp), %xmm2, %xmm2
246; AVX512F-64-NEXT: vpinsrw $4, {{[0-9]+}}(%rsp), %xmm2, %xmm2
247; AVX512F-64-NEXT: vpinsrw $5, {{[0-9]+}}(%rsp), %xmm2, %xmm2
248; AVX512F-64-NEXT: vpinsrw $6, {{[0-9]+}}(%rsp), %xmm2, %xmm2
249; AVX512F-64-NEXT: vpinsrw $7, {{[0-9]+}}(%rsp), %xmm2, %xmm2
250; AVX512F-64-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
251; AVX512F-64-NEXT: retq
252;
253; AVX512BW-32-LABEL: test_buildvector_v32i16:
254; AVX512BW-32: # BB#0:
255; AVX512BW-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
256; AVX512BW-32-NEXT: vpinsrw $1, {{[0-9]+}}(%esp), %xmm0, %xmm0
257; AVX512BW-32-NEXT: vpinsrw $2, {{[0-9]+}}(%esp), %xmm0, %xmm0
258; AVX512BW-32-NEXT: vpinsrw $3, {{[0-9]+}}(%esp), %xmm0, %xmm0
259; AVX512BW-32-NEXT: vpinsrw $4, {{[0-9]+}}(%esp), %xmm0, %xmm0
260; AVX512BW-32-NEXT: vpinsrw $5, {{[0-9]+}}(%esp), %xmm0, %xmm0
261; AVX512BW-32-NEXT: vpinsrw $6, {{[0-9]+}}(%esp), %xmm0, %xmm0
262; AVX512BW-32-NEXT: vpinsrw $7, {{[0-9]+}}(%esp), %xmm0, %xmm0
263; AVX512BW-32-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
264; AVX512BW-32-NEXT: vpinsrw $1, {{[0-9]+}}(%esp), %xmm1, %xmm1
265; AVX512BW-32-NEXT: vpinsrw $2, {{[0-9]+}}(%esp), %xmm1, %xmm1
266; AVX512BW-32-NEXT: vpinsrw $3, {{[0-9]+}}(%esp), %xmm1, %xmm1
267; AVX512BW-32-NEXT: vpinsrw $4, {{[0-9]+}}(%esp), %xmm1, %xmm1
268; AVX512BW-32-NEXT: vpinsrw $5, {{[0-9]+}}(%esp), %xmm1, %xmm1
269; AVX512BW-32-NEXT: vpinsrw $6, {{[0-9]+}}(%esp), %xmm1, %xmm1
270; AVX512BW-32-NEXT: vpinsrw $7, {{[0-9]+}}(%esp), %xmm1, %xmm1
271; AVX512BW-32-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
272; AVX512BW-32-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
273; AVX512BW-32-NEXT: vpinsrw $1, {{[0-9]+}}(%esp), %xmm1, %xmm1
274; AVX512BW-32-NEXT: vpinsrw $2, {{[0-9]+}}(%esp), %xmm1, %xmm1
275; AVX512BW-32-NEXT: vpinsrw $3, {{[0-9]+}}(%esp), %xmm1, %xmm1
276; AVX512BW-32-NEXT: vpinsrw $4, {{[0-9]+}}(%esp), %xmm1, %xmm1
277; AVX512BW-32-NEXT: vpinsrw $5, {{[0-9]+}}(%esp), %xmm1, %xmm1
278; AVX512BW-32-NEXT: vpinsrw $6, {{[0-9]+}}(%esp), %xmm1, %xmm1
279; AVX512BW-32-NEXT: vpinsrw $7, {{[0-9]+}}(%esp), %xmm1, %xmm1
280; AVX512BW-32-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero
281; AVX512BW-32-NEXT: vpinsrw $1, {{[0-9]+}}(%esp), %xmm2, %xmm2
282; AVX512BW-32-NEXT: vpinsrw $2, {{[0-9]+}}(%esp), %xmm2, %xmm2
283; AVX512BW-32-NEXT: vpinsrw $3, {{[0-9]+}}(%esp), %xmm2, %xmm2
284; AVX512BW-32-NEXT: vpinsrw $4, {{[0-9]+}}(%esp), %xmm2, %xmm2
285; AVX512BW-32-NEXT: vpinsrw $5, {{[0-9]+}}(%esp), %xmm2, %xmm2
286; AVX512BW-32-NEXT: vpinsrw $6, {{[0-9]+}}(%esp), %xmm2, %xmm2
287; AVX512BW-32-NEXT: vpinsrw $7, {{[0-9]+}}(%esp), %xmm2, %xmm2
288; AVX512BW-32-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
289; AVX512BW-32-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
290; AVX512BW-32-NEXT: retl
291;
292; AVX512BW-64-LABEL: test_buildvector_v32i16:
293; AVX512BW-64: # BB#0:
294; AVX512BW-64-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
295; AVX512BW-64-NEXT: vpinsrw $1, {{[0-9]+}}(%rsp), %xmm0, %xmm0
296; AVX512BW-64-NEXT: vpinsrw $2, {{[0-9]+}}(%rsp), %xmm0, %xmm0
297; AVX512BW-64-NEXT: vpinsrw $3, {{[0-9]+}}(%rsp), %xmm0, %xmm0
298; AVX512BW-64-NEXT: vpinsrw $4, {{[0-9]+}}(%rsp), %xmm0, %xmm0
299; AVX512BW-64-NEXT: vpinsrw $5, {{[0-9]+}}(%rsp), %xmm0, %xmm0
300; AVX512BW-64-NEXT: vpinsrw $6, {{[0-9]+}}(%rsp), %xmm0, %xmm0
301; AVX512BW-64-NEXT: vpinsrw $7, {{[0-9]+}}(%rsp), %xmm0, %xmm0
302; AVX512BW-64-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
303; AVX512BW-64-NEXT: vpinsrw $1, {{[0-9]+}}(%rsp), %xmm1, %xmm1
304; AVX512BW-64-NEXT: vpinsrw $2, {{[0-9]+}}(%rsp), %xmm1, %xmm1
305; AVX512BW-64-NEXT: vpinsrw $3, {{[0-9]+}}(%rsp), %xmm1, %xmm1
306; AVX512BW-64-NEXT: vpinsrw $4, {{[0-9]+}}(%rsp), %xmm1, %xmm1
307; AVX512BW-64-NEXT: vpinsrw $5, {{[0-9]+}}(%rsp), %xmm1, %xmm1
308; AVX512BW-64-NEXT: vpinsrw $6, {{[0-9]+}}(%rsp), %xmm1, %xmm1
309; AVX512BW-64-NEXT: vpinsrw $7, {{[0-9]+}}(%rsp), %xmm1, %xmm1
310; AVX512BW-64-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
311; AVX512BW-64-NEXT: vmovd %edi, %xmm1
312; AVX512BW-64-NEXT: vpinsrw $1, %esi, %xmm1, %xmm1
313; AVX512BW-64-NEXT: vpinsrw $2, %edx, %xmm1, %xmm1
314; AVX512BW-64-NEXT: vpinsrw $3, %ecx, %xmm1, %xmm1
315; AVX512BW-64-NEXT: vpinsrw $4, %r8d, %xmm1, %xmm1
316; AVX512BW-64-NEXT: vpinsrw $5, %r9d, %xmm1, %xmm1
317; AVX512BW-64-NEXT: vpinsrw $6, {{[0-9]+}}(%rsp), %xmm1, %xmm1
318; AVX512BW-64-NEXT: vpinsrw $7, {{[0-9]+}}(%rsp), %xmm1, %xmm1
319; AVX512BW-64-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero
320; AVX512BW-64-NEXT: vpinsrw $1, {{[0-9]+}}(%rsp), %xmm2, %xmm2
321; AVX512BW-64-NEXT: vpinsrw $2, {{[0-9]+}}(%rsp), %xmm2, %xmm2
322; AVX512BW-64-NEXT: vpinsrw $3, {{[0-9]+}}(%rsp), %xmm2, %xmm2
323; AVX512BW-64-NEXT: vpinsrw $4, {{[0-9]+}}(%rsp), %xmm2, %xmm2
324; AVX512BW-64-NEXT: vpinsrw $5, {{[0-9]+}}(%rsp), %xmm2, %xmm2
325; AVX512BW-64-NEXT: vpinsrw $6, {{[0-9]+}}(%rsp), %xmm2, %xmm2
326; AVX512BW-64-NEXT: vpinsrw $7, {{[0-9]+}}(%rsp), %xmm2, %xmm2
327; AVX512BW-64-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
328; AVX512BW-64-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
329; AVX512BW-64-NEXT: retq
330 %ins0 = insertelement <32 x i16> undef, i16 %a0, i32 0
331 %ins1 = insertelement <32 x i16> %ins0, i16 %a1, i32 1
332 %ins2 = insertelement <32 x i16> %ins1, i16 %a2, i32 2
333 %ins3 = insertelement <32 x i16> %ins2, i16 %a3, i32 3
334 %ins4 = insertelement <32 x i16> %ins3, i16 %a4, i32 4
335 %ins5 = insertelement <32 x i16> %ins4, i16 %a5, i32 5
336 %ins6 = insertelement <32 x i16> %ins5, i16 %a6, i32 6
337 %ins7 = insertelement <32 x i16> %ins6, i16 %a7, i32 7
338 %ins8 = insertelement <32 x i16> %ins7, i16 %a8, i32 8
339 %ins9 = insertelement <32 x i16> %ins8, i16 %a9, i32 9
340 %ins10 = insertelement <32 x i16> %ins9, i16 %a10, i32 10
341 %ins11 = insertelement <32 x i16> %ins10, i16 %a11, i32 11
342 %ins12 = insertelement <32 x i16> %ins11, i16 %a12, i32 12
343 %ins13 = insertelement <32 x i16> %ins12, i16 %a13, i32 13
344 %ins14 = insertelement <32 x i16> %ins13, i16 %a14, i32 14
345 %ins15 = insertelement <32 x i16> %ins14, i16 %a15, i32 15
346 %ins16 = insertelement <32 x i16> %ins15, i16 %a16, i32 16
347 %ins17 = insertelement <32 x i16> %ins16, i16 %a17, i32 17
348 %ins18 = insertelement <32 x i16> %ins17, i16 %a18, i32 18
349 %ins19 = insertelement <32 x i16> %ins18, i16 %a19, i32 19
350 %ins20 = insertelement <32 x i16> %ins19, i16 %a20, i32 20
351 %ins21 = insertelement <32 x i16> %ins20, i16 %a21, i32 21
352 %ins22 = insertelement <32 x i16> %ins21, i16 %a22, i32 22
353 %ins23 = insertelement <32 x i16> %ins22, i16 %a23, i32 23
354 %ins24 = insertelement <32 x i16> %ins23, i16 %a24, i32 24
355 %ins25 = insertelement <32 x i16> %ins24, i16 %a25, i32 25
356 %ins26 = insertelement <32 x i16> %ins25, i16 %a26, i32 26
357 %ins27 = insertelement <32 x i16> %ins26, i16 %a27, i32 27
358 %ins28 = insertelement <32 x i16> %ins27, i16 %a28, i32 28
359 %ins29 = insertelement <32 x i16> %ins28, i16 %a29, i32 29
360 %ins30 = insertelement <32 x i16> %ins29, i16 %a30, i32 30
361 %ins31 = insertelement <32 x i16> %ins30, i16 %a31, i32 31
362 ret <32 x i16> %ins31
363}
364
365define <64 x i8> @test_buildvector_v64i8(i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4, i8 %a5, i8 %a6, i8 %a7, i8 %a8, i8 %a9, i8 %a10, i8 %a11, i8 %a12, i8 %a13, i8 %a14, i8 %a15, i8 %a16, i8 %a17, i8 %a18, i8 %a19, i8 %a20, i8 %a21, i8 %a22, i8 %a23, i8 %a24, i8 %a25, i8 %a26, i8 %a27, i8 %a28, i8 %a29, i8 %a30, i8 %a31, i8 %a32, i8 %a33, i8 %a34, i8 %a35, i8 %a36, i8 %a37, i8 %a38, i8 %a39, i8 %a40, i8 %a41, i8 %a42, i8 %a43, i8 %a44, i8 %a45, i8 %a46, i8 %a47, i8 %a48, i8 %a49, i8 %a50, i8 %a51, i8 %a52, i8 %a53, i8 %a54, i8 %a55, i8 %a56, i8 %a57, i8 %a58, i8 %a59, i8 %a60, i8 %a61, i8 %a62, i8 %a63) {
366; AVX512F-32-LABEL: test_buildvector_v64i8:
367; AVX512F-32: # BB#0:
368; AVX512F-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
369; AVX512F-32-NEXT: vpinsrb $1, {{[0-9]+}}(%esp), %xmm0, %xmm0
370; AVX512F-32-NEXT: vpinsrb $2, {{[0-9]+}}(%esp), %xmm0, %xmm0
371; AVX512F-32-NEXT: vpinsrb $3, {{[0-9]+}}(%esp), %xmm0, %xmm0
372; AVX512F-32-NEXT: vpinsrb $4, {{[0-9]+}}(%esp), %xmm0, %xmm0
373; AVX512F-32-NEXT: vpinsrb $5, {{[0-9]+}}(%esp), %xmm0, %xmm0
374; AVX512F-32-NEXT: vpinsrb $6, {{[0-9]+}}(%esp), %xmm0, %xmm0
375; AVX512F-32-NEXT: vpinsrb $7, {{[0-9]+}}(%esp), %xmm0, %xmm0
376; AVX512F-32-NEXT: vpinsrb $8, {{[0-9]+}}(%esp), %xmm0, %xmm0
377; AVX512F-32-NEXT: vpinsrb $9, {{[0-9]+}}(%esp), %xmm0, %xmm0
378; AVX512F-32-NEXT: vpinsrb $10, {{[0-9]+}}(%esp), %xmm0, %xmm0
379; AVX512F-32-NEXT: vpinsrb $11, {{[0-9]+}}(%esp), %xmm0, %xmm0
380; AVX512F-32-NEXT: vpinsrb $12, {{[0-9]+}}(%esp), %xmm0, %xmm0
381; AVX512F-32-NEXT: vpinsrb $13, {{[0-9]+}}(%esp), %xmm0, %xmm0
382; AVX512F-32-NEXT: vpinsrb $14, {{[0-9]+}}(%esp), %xmm0, %xmm0
383; AVX512F-32-NEXT: vpinsrb $15, {{[0-9]+}}(%esp), %xmm0, %xmm0
384; AVX512F-32-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
385; AVX512F-32-NEXT: vpinsrb $1, {{[0-9]+}}(%esp), %xmm1, %xmm1
386; AVX512F-32-NEXT: vpinsrb $2, {{[0-9]+}}(%esp), %xmm1, %xmm1
387; AVX512F-32-NEXT: vpinsrb $3, {{[0-9]+}}(%esp), %xmm1, %xmm1
388; AVX512F-32-NEXT: vpinsrb $4, {{[0-9]+}}(%esp), %xmm1, %xmm1
389; AVX512F-32-NEXT: vpinsrb $5, {{[0-9]+}}(%esp), %xmm1, %xmm1
390; AVX512F-32-NEXT: vpinsrb $6, {{[0-9]+}}(%esp), %xmm1, %xmm1
391; AVX512F-32-NEXT: vpinsrb $7, {{[0-9]+}}(%esp), %xmm1, %xmm1
392; AVX512F-32-NEXT: vpinsrb $8, {{[0-9]+}}(%esp), %xmm1, %xmm1
393; AVX512F-32-NEXT: vpinsrb $9, {{[0-9]+}}(%esp), %xmm1, %xmm1
394; AVX512F-32-NEXT: vpinsrb $10, {{[0-9]+}}(%esp), %xmm1, %xmm1
395; AVX512F-32-NEXT: vpinsrb $11, {{[0-9]+}}(%esp), %xmm1, %xmm1
396; AVX512F-32-NEXT: vpinsrb $12, {{[0-9]+}}(%esp), %xmm1, %xmm1
397; AVX512F-32-NEXT: vpinsrb $13, {{[0-9]+}}(%esp), %xmm1, %xmm1
398; AVX512F-32-NEXT: vpinsrb $14, {{[0-9]+}}(%esp), %xmm1, %xmm1
399; AVX512F-32-NEXT: vpinsrb $15, {{[0-9]+}}(%esp), %xmm1, %xmm1
400; AVX512F-32-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
401; AVX512F-32-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
402; AVX512F-32-NEXT: vpinsrb $1, {{[0-9]+}}(%esp), %xmm1, %xmm1
403; AVX512F-32-NEXT: vpinsrb $2, {{[0-9]+}}(%esp), %xmm1, %xmm1
404; AVX512F-32-NEXT: vpinsrb $3, {{[0-9]+}}(%esp), %xmm1, %xmm1
405; AVX512F-32-NEXT: vpinsrb $4, {{[0-9]+}}(%esp), %xmm1, %xmm1
406; AVX512F-32-NEXT: vpinsrb $5, {{[0-9]+}}(%esp), %xmm1, %xmm1
407; AVX512F-32-NEXT: vpinsrb $6, {{[0-9]+}}(%esp), %xmm1, %xmm1
408; AVX512F-32-NEXT: vpinsrb $7, {{[0-9]+}}(%esp), %xmm1, %xmm1
409; AVX512F-32-NEXT: vpinsrb $8, {{[0-9]+}}(%esp), %xmm1, %xmm1
410; AVX512F-32-NEXT: vpinsrb $9, {{[0-9]+}}(%esp), %xmm1, %xmm1
411; AVX512F-32-NEXT: vpinsrb $10, {{[0-9]+}}(%esp), %xmm1, %xmm1
412; AVX512F-32-NEXT: vpinsrb $11, {{[0-9]+}}(%esp), %xmm1, %xmm1
413; AVX512F-32-NEXT: vpinsrb $12, {{[0-9]+}}(%esp), %xmm1, %xmm1
414; AVX512F-32-NEXT: vpinsrb $13, {{[0-9]+}}(%esp), %xmm1, %xmm1
415; AVX512F-32-NEXT: vpinsrb $14, {{[0-9]+}}(%esp), %xmm1, %xmm1
416; AVX512F-32-NEXT: vpinsrb $15, {{[0-9]+}}(%esp), %xmm1, %xmm1
417; AVX512F-32-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero
418; AVX512F-32-NEXT: vpinsrb $1, {{[0-9]+}}(%esp), %xmm2, %xmm2
419; AVX512F-32-NEXT: vpinsrb $2, {{[0-9]+}}(%esp), %xmm2, %xmm2
420; AVX512F-32-NEXT: vpinsrb $3, {{[0-9]+}}(%esp), %xmm2, %xmm2
421; AVX512F-32-NEXT: vpinsrb $4, {{[0-9]+}}(%esp), %xmm2, %xmm2
422; AVX512F-32-NEXT: vpinsrb $5, {{[0-9]+}}(%esp), %xmm2, %xmm2
423; AVX512F-32-NEXT: vpinsrb $6, {{[0-9]+}}(%esp), %xmm2, %xmm2
424; AVX512F-32-NEXT: vpinsrb $7, {{[0-9]+}}(%esp), %xmm2, %xmm2
425; AVX512F-32-NEXT: vpinsrb $8, {{[0-9]+}}(%esp), %xmm2, %xmm2
426; AVX512F-32-NEXT: vpinsrb $9, {{[0-9]+}}(%esp), %xmm2, %xmm2
427; AVX512F-32-NEXT: vpinsrb $10, {{[0-9]+}}(%esp), %xmm2, %xmm2
428; AVX512F-32-NEXT: vpinsrb $11, {{[0-9]+}}(%esp), %xmm2, %xmm2
429; AVX512F-32-NEXT: vpinsrb $12, {{[0-9]+}}(%esp), %xmm2, %xmm2
430; AVX512F-32-NEXT: vpinsrb $13, {{[0-9]+}}(%esp), %xmm2, %xmm2
431; AVX512F-32-NEXT: vpinsrb $14, {{[0-9]+}}(%esp), %xmm2, %xmm2
432; AVX512F-32-NEXT: vpinsrb $15, {{[0-9]+}}(%esp), %xmm2, %xmm2
433; AVX512F-32-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
434; AVX512F-32-NEXT: retl
435;
436; AVX512F-64-LABEL: test_buildvector_v64i8:
437; AVX512F-64: # BB#0:
438; AVX512F-64-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
439; AVX512F-64-NEXT: vpinsrb $1, {{[0-9]+}}(%rsp), %xmm0, %xmm0
440; AVX512F-64-NEXT: vpinsrb $2, {{[0-9]+}}(%rsp), %xmm0, %xmm0
441; AVX512F-64-NEXT: vpinsrb $3, {{[0-9]+}}(%rsp), %xmm0, %xmm0
442; AVX512F-64-NEXT: vpinsrb $4, {{[0-9]+}}(%rsp), %xmm0, %xmm0
443; AVX512F-64-NEXT: vpinsrb $5, {{[0-9]+}}(%rsp), %xmm0, %xmm0
444; AVX512F-64-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm0, %xmm0
445; AVX512F-64-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm0, %xmm0
446; AVX512F-64-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm0, %xmm0
447; AVX512F-64-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm0, %xmm0
448; AVX512F-64-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm0, %xmm0
449; AVX512F-64-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm0, %xmm0
450; AVX512F-64-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm0, %xmm0
451; AVX512F-64-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm0, %xmm0
452; AVX512F-64-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm0, %xmm0
453; AVX512F-64-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm0, %xmm0
454; AVX512F-64-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
455; AVX512F-64-NEXT: vpinsrb $1, {{[0-9]+}}(%rsp), %xmm1, %xmm1
456; AVX512F-64-NEXT: vpinsrb $2, {{[0-9]+}}(%rsp), %xmm1, %xmm1
457; AVX512F-64-NEXT: vpinsrb $3, {{[0-9]+}}(%rsp), %xmm1, %xmm1
458; AVX512F-64-NEXT: vpinsrb $4, {{[0-9]+}}(%rsp), %xmm1, %xmm1
459; AVX512F-64-NEXT: vpinsrb $5, {{[0-9]+}}(%rsp), %xmm1, %xmm1
460; AVX512F-64-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm1, %xmm1
461; AVX512F-64-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm1, %xmm1
462; AVX512F-64-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm1, %xmm1
463; AVX512F-64-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm1, %xmm1
464; AVX512F-64-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm1, %xmm1
465; AVX512F-64-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm1, %xmm1
466; AVX512F-64-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm1, %xmm1
467; AVX512F-64-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm1, %xmm1
468; AVX512F-64-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm1, %xmm1
469; AVX512F-64-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm1, %xmm1
470; AVX512F-64-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm1
471; AVX512F-64-NEXT: vmovd %edi, %xmm0
472; AVX512F-64-NEXT: vpinsrb $1, %esi, %xmm0, %xmm0
473; AVX512F-64-NEXT: vpinsrb $2, %edx, %xmm0, %xmm0
474; AVX512F-64-NEXT: vpinsrb $3, %ecx, %xmm0, %xmm0
475; AVX512F-64-NEXT: vpinsrb $4, %r8d, %xmm0, %xmm0
476; AVX512F-64-NEXT: vpinsrb $5, %r9d, %xmm0, %xmm0
477; AVX512F-64-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm0, %xmm0
478; AVX512F-64-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm0, %xmm0
479; AVX512F-64-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm0, %xmm0
480; AVX512F-64-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm0, %xmm0
481; AVX512F-64-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm0, %xmm0
482; AVX512F-64-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm0, %xmm0
483; AVX512F-64-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm0, %xmm0
484; AVX512F-64-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm0, %xmm0
485; AVX512F-64-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm0, %xmm0
486; AVX512F-64-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm0, %xmm0
487; AVX512F-64-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero
488; AVX512F-64-NEXT: vpinsrb $1, {{[0-9]+}}(%rsp), %xmm2, %xmm2
489; AVX512F-64-NEXT: vpinsrb $2, {{[0-9]+}}(%rsp), %xmm2, %xmm2
490; AVX512F-64-NEXT: vpinsrb $3, {{[0-9]+}}(%rsp), %xmm2, %xmm2
491; AVX512F-64-NEXT: vpinsrb $4, {{[0-9]+}}(%rsp), %xmm2, %xmm2
492; AVX512F-64-NEXT: vpinsrb $5, {{[0-9]+}}(%rsp), %xmm2, %xmm2
493; AVX512F-64-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm2, %xmm2
494; AVX512F-64-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm2, %xmm2
495; AVX512F-64-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm2, %xmm2
496; AVX512F-64-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm2, %xmm2
497; AVX512F-64-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm2, %xmm2
498; AVX512F-64-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm2, %xmm2
499; AVX512F-64-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm2, %xmm2
500; AVX512F-64-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm2, %xmm2
501; AVX512F-64-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm2, %xmm2
502; AVX512F-64-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm2, %xmm2
503; AVX512F-64-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
504; AVX512F-64-NEXT: retq
505;
506; AVX512BW-32-LABEL: test_buildvector_v64i8:
507; AVX512BW-32: # BB#0:
508; AVX512BW-32-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
509; AVX512BW-32-NEXT: vpinsrb $1, {{[0-9]+}}(%esp), %xmm0, %xmm0
510; AVX512BW-32-NEXT: vpinsrb $2, {{[0-9]+}}(%esp), %xmm0, %xmm0
511; AVX512BW-32-NEXT: vpinsrb $3, {{[0-9]+}}(%esp), %xmm0, %xmm0
512; AVX512BW-32-NEXT: vpinsrb $4, {{[0-9]+}}(%esp), %xmm0, %xmm0
513; AVX512BW-32-NEXT: vpinsrb $5, {{[0-9]+}}(%esp), %xmm0, %xmm0
514; AVX512BW-32-NEXT: vpinsrb $6, {{[0-9]+}}(%esp), %xmm0, %xmm0
515; AVX512BW-32-NEXT: vpinsrb $7, {{[0-9]+}}(%esp), %xmm0, %xmm0
516; AVX512BW-32-NEXT: vpinsrb $8, {{[0-9]+}}(%esp), %xmm0, %xmm0
517; AVX512BW-32-NEXT: vpinsrb $9, {{[0-9]+}}(%esp), %xmm0, %xmm0
518; AVX512BW-32-NEXT: vpinsrb $10, {{[0-9]+}}(%esp), %xmm0, %xmm0
519; AVX512BW-32-NEXT: vpinsrb $11, {{[0-9]+}}(%esp), %xmm0, %xmm0
520; AVX512BW-32-NEXT: vpinsrb $12, {{[0-9]+}}(%esp), %xmm0, %xmm0
521; AVX512BW-32-NEXT: vpinsrb $13, {{[0-9]+}}(%esp), %xmm0, %xmm0
522; AVX512BW-32-NEXT: vpinsrb $14, {{[0-9]+}}(%esp), %xmm0, %xmm0
523; AVX512BW-32-NEXT: vpinsrb $15, {{[0-9]+}}(%esp), %xmm0, %xmm0
524; AVX512BW-32-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
525; AVX512BW-32-NEXT: vpinsrb $1, {{[0-9]+}}(%esp), %xmm1, %xmm1
526; AVX512BW-32-NEXT: vpinsrb $2, {{[0-9]+}}(%esp), %xmm1, %xmm1
527; AVX512BW-32-NEXT: vpinsrb $3, {{[0-9]+}}(%esp), %xmm1, %xmm1
528; AVX512BW-32-NEXT: vpinsrb $4, {{[0-9]+}}(%esp), %xmm1, %xmm1
529; AVX512BW-32-NEXT: vpinsrb $5, {{[0-9]+}}(%esp), %xmm1, %xmm1
530; AVX512BW-32-NEXT: vpinsrb $6, {{[0-9]+}}(%esp), %xmm1, %xmm1
531; AVX512BW-32-NEXT: vpinsrb $7, {{[0-9]+}}(%esp), %xmm1, %xmm1
532; AVX512BW-32-NEXT: vpinsrb $8, {{[0-9]+}}(%esp), %xmm1, %xmm1
533; AVX512BW-32-NEXT: vpinsrb $9, {{[0-9]+}}(%esp), %xmm1, %xmm1
534; AVX512BW-32-NEXT: vpinsrb $10, {{[0-9]+}}(%esp), %xmm1, %xmm1
535; AVX512BW-32-NEXT: vpinsrb $11, {{[0-9]+}}(%esp), %xmm1, %xmm1
536; AVX512BW-32-NEXT: vpinsrb $12, {{[0-9]+}}(%esp), %xmm1, %xmm1
537; AVX512BW-32-NEXT: vpinsrb $13, {{[0-9]+}}(%esp), %xmm1, %xmm1
538; AVX512BW-32-NEXT: vpinsrb $14, {{[0-9]+}}(%esp), %xmm1, %xmm1
539; AVX512BW-32-NEXT: vpinsrb $15, {{[0-9]+}}(%esp), %xmm1, %xmm1
540; AVX512BW-32-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
541; AVX512BW-32-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
542; AVX512BW-32-NEXT: vpinsrb $1, {{[0-9]+}}(%esp), %xmm1, %xmm1
543; AVX512BW-32-NEXT: vpinsrb $2, {{[0-9]+}}(%esp), %xmm1, %xmm1
544; AVX512BW-32-NEXT: vpinsrb $3, {{[0-9]+}}(%esp), %xmm1, %xmm1
545; AVX512BW-32-NEXT: vpinsrb $4, {{[0-9]+}}(%esp), %xmm1, %xmm1
546; AVX512BW-32-NEXT: vpinsrb $5, {{[0-9]+}}(%esp), %xmm1, %xmm1
547; AVX512BW-32-NEXT: vpinsrb $6, {{[0-9]+}}(%esp), %xmm1, %xmm1
548; AVX512BW-32-NEXT: vpinsrb $7, {{[0-9]+}}(%esp), %xmm1, %xmm1
549; AVX512BW-32-NEXT: vpinsrb $8, {{[0-9]+}}(%esp), %xmm1, %xmm1
550; AVX512BW-32-NEXT: vpinsrb $9, {{[0-9]+}}(%esp), %xmm1, %xmm1
551; AVX512BW-32-NEXT: vpinsrb $10, {{[0-9]+}}(%esp), %xmm1, %xmm1
552; AVX512BW-32-NEXT: vpinsrb $11, {{[0-9]+}}(%esp), %xmm1, %xmm1
553; AVX512BW-32-NEXT: vpinsrb $12, {{[0-9]+}}(%esp), %xmm1, %xmm1
554; AVX512BW-32-NEXT: vpinsrb $13, {{[0-9]+}}(%esp), %xmm1, %xmm1
555; AVX512BW-32-NEXT: vpinsrb $14, {{[0-9]+}}(%esp), %xmm1, %xmm1
556; AVX512BW-32-NEXT: vpinsrb $15, {{[0-9]+}}(%esp), %xmm1, %xmm1
557; AVX512BW-32-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero
558; AVX512BW-32-NEXT: vpinsrb $1, {{[0-9]+}}(%esp), %xmm2, %xmm2
559; AVX512BW-32-NEXT: vpinsrb $2, {{[0-9]+}}(%esp), %xmm2, %xmm2
560; AVX512BW-32-NEXT: vpinsrb $3, {{[0-9]+}}(%esp), %xmm2, %xmm2
561; AVX512BW-32-NEXT: vpinsrb $4, {{[0-9]+}}(%esp), %xmm2, %xmm2
562; AVX512BW-32-NEXT: vpinsrb $5, {{[0-9]+}}(%esp), %xmm2, %xmm2
563; AVX512BW-32-NEXT: vpinsrb $6, {{[0-9]+}}(%esp), %xmm2, %xmm2
564; AVX512BW-32-NEXT: vpinsrb $7, {{[0-9]+}}(%esp), %xmm2, %xmm2
565; AVX512BW-32-NEXT: vpinsrb $8, {{[0-9]+}}(%esp), %xmm2, %xmm2
566; AVX512BW-32-NEXT: vpinsrb $9, {{[0-9]+}}(%esp), %xmm2, %xmm2
567; AVX512BW-32-NEXT: vpinsrb $10, {{[0-9]+}}(%esp), %xmm2, %xmm2
568; AVX512BW-32-NEXT: vpinsrb $11, {{[0-9]+}}(%esp), %xmm2, %xmm2
569; AVX512BW-32-NEXT: vpinsrb $12, {{[0-9]+}}(%esp), %xmm2, %xmm2
570; AVX512BW-32-NEXT: vpinsrb $13, {{[0-9]+}}(%esp), %xmm2, %xmm2
571; AVX512BW-32-NEXT: vpinsrb $14, {{[0-9]+}}(%esp), %xmm2, %xmm2
572; AVX512BW-32-NEXT: vpinsrb $15, {{[0-9]+}}(%esp), %xmm2, %xmm2
573; AVX512BW-32-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
574; AVX512BW-32-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
575; AVX512BW-32-NEXT: retl
576;
577; AVX512BW-64-LABEL: test_buildvector_v64i8:
578; AVX512BW-64: # BB#0:
579; AVX512BW-64-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
580; AVX512BW-64-NEXT: vpinsrb $1, {{[0-9]+}}(%rsp), %xmm0, %xmm0
581; AVX512BW-64-NEXT: vpinsrb $2, {{[0-9]+}}(%rsp), %xmm0, %xmm0
582; AVX512BW-64-NEXT: vpinsrb $3, {{[0-9]+}}(%rsp), %xmm0, %xmm0
583; AVX512BW-64-NEXT: vpinsrb $4, {{[0-9]+}}(%rsp), %xmm0, %xmm0
584; AVX512BW-64-NEXT: vpinsrb $5, {{[0-9]+}}(%rsp), %xmm0, %xmm0
585; AVX512BW-64-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm0, %xmm0
586; AVX512BW-64-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm0, %xmm0
587; AVX512BW-64-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm0, %xmm0
588; AVX512BW-64-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm0, %xmm0
589; AVX512BW-64-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm0, %xmm0
590; AVX512BW-64-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm0, %xmm0
591; AVX512BW-64-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm0, %xmm0
592; AVX512BW-64-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm0, %xmm0
593; AVX512BW-64-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm0, %xmm0
594; AVX512BW-64-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm0, %xmm0
595; AVX512BW-64-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
596; AVX512BW-64-NEXT: vpinsrb $1, {{[0-9]+}}(%rsp), %xmm1, %xmm1
597; AVX512BW-64-NEXT: vpinsrb $2, {{[0-9]+}}(%rsp), %xmm1, %xmm1
598; AVX512BW-64-NEXT: vpinsrb $3, {{[0-9]+}}(%rsp), %xmm1, %xmm1
599; AVX512BW-64-NEXT: vpinsrb $4, {{[0-9]+}}(%rsp), %xmm1, %xmm1
600; AVX512BW-64-NEXT: vpinsrb $5, {{[0-9]+}}(%rsp), %xmm1, %xmm1
601; AVX512BW-64-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm1, %xmm1
602; AVX512BW-64-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm1, %xmm1
603; AVX512BW-64-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm1, %xmm1
604; AVX512BW-64-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm1, %xmm1
605; AVX512BW-64-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm1, %xmm1
606; AVX512BW-64-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm1, %xmm1
607; AVX512BW-64-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm1, %xmm1
608; AVX512BW-64-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm1, %xmm1
609; AVX512BW-64-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm1, %xmm1
610; AVX512BW-64-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm1, %xmm1
611; AVX512BW-64-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
612; AVX512BW-64-NEXT: vmovd %edi, %xmm1
613; AVX512BW-64-NEXT: vpinsrb $1, %esi, %xmm1, %xmm1
614; AVX512BW-64-NEXT: vpinsrb $2, %edx, %xmm1, %xmm1
615; AVX512BW-64-NEXT: vpinsrb $3, %ecx, %xmm1, %xmm1
616; AVX512BW-64-NEXT: vpinsrb $4, %r8d, %xmm1, %xmm1
617; AVX512BW-64-NEXT: vpinsrb $5, %r9d, %xmm1, %xmm1
618; AVX512BW-64-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm1, %xmm1
619; AVX512BW-64-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm1, %xmm1
620; AVX512BW-64-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm1, %xmm1
621; AVX512BW-64-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm1, %xmm1
622; AVX512BW-64-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm1, %xmm1
623; AVX512BW-64-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm1, %xmm1
624; AVX512BW-64-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm1, %xmm1
625; AVX512BW-64-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm1, %xmm1
626; AVX512BW-64-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm1, %xmm1
627; AVX512BW-64-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm1, %xmm1
628; AVX512BW-64-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero
629; AVX512BW-64-NEXT: vpinsrb $1, {{[0-9]+}}(%rsp), %xmm2, %xmm2
630; AVX512BW-64-NEXT: vpinsrb $2, {{[0-9]+}}(%rsp), %xmm2, %xmm2
631; AVX512BW-64-NEXT: vpinsrb $3, {{[0-9]+}}(%rsp), %xmm2, %xmm2
632; AVX512BW-64-NEXT: vpinsrb $4, {{[0-9]+}}(%rsp), %xmm2, %xmm2
633; AVX512BW-64-NEXT: vpinsrb $5, {{[0-9]+}}(%rsp), %xmm2, %xmm2
634; AVX512BW-64-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm2, %xmm2
635; AVX512BW-64-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm2, %xmm2
636; AVX512BW-64-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm2, %xmm2
637; AVX512BW-64-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm2, %xmm2
638; AVX512BW-64-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm2, %xmm2
639; AVX512BW-64-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm2, %xmm2
640; AVX512BW-64-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm2, %xmm2
641; AVX512BW-64-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm2, %xmm2
642; AVX512BW-64-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm2, %xmm2
643; AVX512BW-64-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm2, %xmm2
644; AVX512BW-64-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
645; AVX512BW-64-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
646; AVX512BW-64-NEXT: retq
647 %ins0 = insertelement <64 x i8> undef, i8 %a0, i32 0
648 %ins1 = insertelement <64 x i8> %ins0, i8 %a1, i32 1
649 %ins2 = insertelement <64 x i8> %ins1, i8 %a2, i32 2
650 %ins3 = insertelement <64 x i8> %ins2, i8 %a3, i32 3
651 %ins4 = insertelement <64 x i8> %ins3, i8 %a4, i32 4
652 %ins5 = insertelement <64 x i8> %ins4, i8 %a5, i32 5
653 %ins6 = insertelement <64 x i8> %ins5, i8 %a6, i32 6
654 %ins7 = insertelement <64 x i8> %ins6, i8 %a7, i32 7
655 %ins8 = insertelement <64 x i8> %ins7, i8 %a8, i32 8
656 %ins9 = insertelement <64 x i8> %ins8, i8 %a9, i32 9
657 %ins10 = insertelement <64 x i8> %ins9, i8 %a10, i32 10
658 %ins11 = insertelement <64 x i8> %ins10, i8 %a11, i32 11
659 %ins12 = insertelement <64 x i8> %ins11, i8 %a12, i32 12
660 %ins13 = insertelement <64 x i8> %ins12, i8 %a13, i32 13
661 %ins14 = insertelement <64 x i8> %ins13, i8 %a14, i32 14
662 %ins15 = insertelement <64 x i8> %ins14, i8 %a15, i32 15
663 %ins16 = insertelement <64 x i8> %ins15, i8 %a16, i32 16
664 %ins17 = insertelement <64 x i8> %ins16, i8 %a17, i32 17
665 %ins18 = insertelement <64 x i8> %ins17, i8 %a18, i32 18
666 %ins19 = insertelement <64 x i8> %ins18, i8 %a19, i32 19
667 %ins20 = insertelement <64 x i8> %ins19, i8 %a20, i32 20
668 %ins21 = insertelement <64 x i8> %ins20, i8 %a21, i32 21
669 %ins22 = insertelement <64 x i8> %ins21, i8 %a22, i32 22
670 %ins23 = insertelement <64 x i8> %ins22, i8 %a23, i32 23
671 %ins24 = insertelement <64 x i8> %ins23, i8 %a24, i32 24
672 %ins25 = insertelement <64 x i8> %ins24, i8 %a25, i32 25
673 %ins26 = insertelement <64 x i8> %ins25, i8 %a26, i32 26
674 %ins27 = insertelement <64 x i8> %ins26, i8 %a27, i32 27
675 %ins28 = insertelement <64 x i8> %ins27, i8 %a28, i32 28
676 %ins29 = insertelement <64 x i8> %ins28, i8 %a29, i32 29
677 %ins30 = insertelement <64 x i8> %ins29, i8 %a30, i32 30
678 %ins31 = insertelement <64 x i8> %ins30, i8 %a31, i32 31
679 %ins32 = insertelement <64 x i8> %ins31, i8 %a32, i32 32
680 %ins33 = insertelement <64 x i8> %ins32, i8 %a33, i32 33
681 %ins34 = insertelement <64 x i8> %ins33, i8 %a34, i32 34
682 %ins35 = insertelement <64 x i8> %ins34, i8 %a35, i32 35
683 %ins36 = insertelement <64 x i8> %ins35, i8 %a36, i32 36
684 %ins37 = insertelement <64 x i8> %ins36, i8 %a37, i32 37
685 %ins38 = insertelement <64 x i8> %ins37, i8 %a38, i32 38
686 %ins39 = insertelement <64 x i8> %ins38, i8 %a39, i32 39
687 %ins40 = insertelement <64 x i8> %ins39, i8 %a40, i32 40
688 %ins41 = insertelement <64 x i8> %ins40, i8 %a41, i32 41
689 %ins42 = insertelement <64 x i8> %ins41, i8 %a42, i32 42
690 %ins43 = insertelement <64 x i8> %ins42, i8 %a43, i32 43
691 %ins44 = insertelement <64 x i8> %ins43, i8 %a44, i32 44
692 %ins45 = insertelement <64 x i8> %ins44, i8 %a45, i32 45
693 %ins46 = insertelement <64 x i8> %ins45, i8 %a46, i32 46
694 %ins47 = insertelement <64 x i8> %ins46, i8 %a47, i32 47
695 %ins48 = insertelement <64 x i8> %ins47, i8 %a48, i32 48
696 %ins49 = insertelement <64 x i8> %ins48, i8 %a49, i32 49
697 %ins50 = insertelement <64 x i8> %ins49, i8 %a50, i32 50
698 %ins51 = insertelement <64 x i8> %ins50, i8 %a51, i32 51
699 %ins52 = insertelement <64 x i8> %ins51, i8 %a52, i32 52
700 %ins53 = insertelement <64 x i8> %ins52, i8 %a53, i32 53
701 %ins54 = insertelement <64 x i8> %ins53, i8 %a54, i32 54
702 %ins55 = insertelement <64 x i8> %ins54, i8 %a55, i32 55
703 %ins56 = insertelement <64 x i8> %ins55, i8 %a56, i32 56
704 %ins57 = insertelement <64 x i8> %ins56, i8 %a57, i32 57
705 %ins58 = insertelement <64 x i8> %ins57, i8 %a58, i32 58
706 %ins59 = insertelement <64 x i8> %ins58, i8 %a59, i32 59
707 %ins60 = insertelement <64 x i8> %ins59, i8 %a60, i32 60
708 %ins61 = insertelement <64 x i8> %ins60, i8 %a61, i32 61
709 %ins62 = insertelement <64 x i8> %ins61, i8 %a62, i32 62
710 %ins63 = insertelement <64 x i8> %ins62, i8 %a63, i32 63
711 ret <64 x i8> %ins63
712}