blob: 6f0e008a6557938983870ed77d39c32bd9f1117c [file] [log] [blame]
Artur Pilipenko41c00052017-01-25 08:53:31 +00001; RUN: llc < %s -mtriple=armeb-unknown | FileCheck %s
2; RUN: llc < %s -mtriple=armv6eb-unknown | FileCheck %s --check-prefix=CHECK-ARMv6
3
4; i8* p; // p is 4 byte aligned
5; ((i32) p[0] << 24) | ((i32) p[1] << 16) | ((i32) p[2] << 8) | (i32) p[3]
6define i32 @load_i32_by_i8_big_endian(i32* %arg) {
7; CHECK-LABEL: load_i32_by_i8_big_endian:
8; CHECK: ldr r0, [r0]
9; CHECK-NEXT: mov pc, lr
10
11; CHECK-ARMv6-LABEL: load_i32_by_i8_big_endian:
12; CHECK-ARMv6: ldr r0, [r0]
13; CHECK-ARMv6-NEXT: bx lr
14 %tmp = bitcast i32* %arg to i8*
15 %tmp1 = load i8, i8* %tmp, align 4
16 %tmp2 = zext i8 %tmp1 to i32
17 %tmp3 = shl nuw nsw i32 %tmp2, 24
18 %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 1
19 %tmp5 = load i8, i8* %tmp4, align 1
20 %tmp6 = zext i8 %tmp5 to i32
21 %tmp7 = shl nuw nsw i32 %tmp6, 16
22 %tmp8 = or i32 %tmp7, %tmp3
23 %tmp9 = getelementptr inbounds i8, i8* %tmp, i32 2
24 %tmp10 = load i8, i8* %tmp9, align 1
25 %tmp11 = zext i8 %tmp10 to i32
26 %tmp12 = shl nuw nsw i32 %tmp11, 8
27 %tmp13 = or i32 %tmp8, %tmp12
28 %tmp14 = getelementptr inbounds i8, i8* %tmp, i32 3
29 %tmp15 = load i8, i8* %tmp14, align 1
30 %tmp16 = zext i8 %tmp15 to i32
31 %tmp17 = or i32 %tmp13, %tmp16
32 ret i32 %tmp17
33}
34
35; i8* p; // p is 4 byte aligned
36; (i32) p[0] | ((i32) p[1] << 8) | ((i32) p[2] << 16) | ((i32) p[3] << 24)
37define i32 @load_i32_by_i8_bswap(i32* %arg) {
38; BSWAP is not supported by 32 bit target
39; CHECK-LABEL: load_i32_by_i8_bswap:
40; CHECK: ldr r0, [r0]
41; CHECK: and
42; CHECK-NEXT: and
43; CHECK-NEXT: orr
44; CHECK-NEXT: orr
45; CHECK-NEXT: orr
46; CHECK-NEXT: mov pc, lr
47
48; CHECK-ARMv6-LABEL: load_i32_by_i8_bswap:
49; CHECK-ARMv6: ldr r0, [r0]
50; CHECK-ARMv6-NEXT: rev r0, r0
51; CHECK-ARMv6-NEXT: bx lr
52 %tmp = bitcast i32* %arg to i8*
53 %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 0
54 %tmp2 = load i8, i8* %tmp, align 4
55 %tmp3 = zext i8 %tmp2 to i32
56 %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 1
57 %tmp5 = load i8, i8* %tmp4, align 1
58 %tmp6 = zext i8 %tmp5 to i32
59 %tmp7 = shl nuw nsw i32 %tmp6, 8
60 %tmp8 = or i32 %tmp7, %tmp3
61 %tmp9 = getelementptr inbounds i8, i8* %tmp, i32 2
62 %tmp10 = load i8, i8* %tmp9, align 1
63 %tmp11 = zext i8 %tmp10 to i32
64 %tmp12 = shl nuw nsw i32 %tmp11, 16
65 %tmp13 = or i32 %tmp8, %tmp12
66 %tmp14 = getelementptr inbounds i8, i8* %tmp, i32 3
67 %tmp15 = load i8, i8* %tmp14, align 1
68 %tmp16 = zext i8 %tmp15 to i32
69 %tmp17 = shl nuw nsw i32 %tmp16, 24
70 %tmp18 = or i32 %tmp13, %tmp17
71 ret i32 %tmp18
72}
73
74; i8* p; // p is 4 byte aligned
75; ((i32) (((i16) p[0] << 8) | (i16) p[1]) << 16) | (i32) (((i16) p[3] << 8) | (i16) p[4])
76define i32 @load_i32_by_i16_by_i8_big_endian(i32* %arg) {
77; CHECK-LABEL: load_i32_by_i16_by_i8_big_endian:
78; CHECK: ldr r0, [r0]
79; CHECK-NEXT: mov pc, lr
80
81; CHECK-ARMv6-LABEL: load_i32_by_i16_by_i8_big_endian:
82; CHECK-ARMv6: ldr r0, [r0]
83; CHECK-ARMv6-NEXT: bx lr
84 %tmp = bitcast i32* %arg to i8*
85 %tmp1 = load i8, i8* %tmp, align 4
86 %tmp2 = zext i8 %tmp1 to i16
87 %tmp3 = getelementptr inbounds i8, i8* %tmp, i32 1
88 %tmp4 = load i8, i8* %tmp3, align 1
89 %tmp5 = zext i8 %tmp4 to i16
90 %tmp6 = shl nuw nsw i16 %tmp2, 8
91 %tmp7 = or i16 %tmp6, %tmp5
92 %tmp8 = getelementptr inbounds i8, i8* %tmp, i32 2
93 %tmp9 = load i8, i8* %tmp8, align 1
94 %tmp10 = zext i8 %tmp9 to i16
95 %tmp11 = getelementptr inbounds i8, i8* %tmp, i32 3
96 %tmp12 = load i8, i8* %tmp11, align 1
97 %tmp13 = zext i8 %tmp12 to i16
98 %tmp14 = shl nuw nsw i16 %tmp10, 8
99 %tmp15 = or i16 %tmp14, %tmp13
100 %tmp16 = zext i16 %tmp7 to i32
101 %tmp17 = zext i16 %tmp15 to i32
102 %tmp18 = shl nuw nsw i32 %tmp16, 16
103 %tmp19 = or i32 %tmp18, %tmp17
104 ret i32 %tmp19
105}
106
107; i16* p; // p is 4 byte aligned
108; ((i32) p[0] << 16) | (i32) p[1]
109define i32 @load_i32_by_i16(i32* %arg) {
110; CHECK-LABEL: load_i32_by_i16:
111; CHECK: ldr r0, [r0]
112; CHECK-NEXT: mov pc, lr
113
114; CHECK-ARMv6-LABEL: load_i32_by_i16:
115; CHECK-ARMv6: ldr r0, [r0]
116; CHECK-ARMv6-NEXT: bx lr
117 %tmp = bitcast i32* %arg to i16*
118 %tmp1 = load i16, i16* %tmp, align 4
119 %tmp2 = zext i16 %tmp1 to i32
120 %tmp3 = getelementptr inbounds i16, i16* %tmp, i32 1
121 %tmp4 = load i16, i16* %tmp3, align 1
122 %tmp5 = zext i16 %tmp4 to i32
123 %tmp6 = shl nuw nsw i32 %tmp2, 16
124 %tmp7 = or i32 %tmp6, %tmp5
125 ret i32 %tmp7
126}
127
128; i16* p_16; // p_16 is 4 byte aligned
129; i8* p_8 = (i8*) p_16;
130; (i32) (p_16[0] << 16) | ((i32) p[2] << 8) | (i32) p[3]
131define i32 @load_i32_by_i16_i8(i32* %arg) {
132; CHECK-LABEL: load_i32_by_i16_i8:
133; CHECK: ldr r0, [r0]
134; CHECK-NEXT: mov pc, lr
135
136; CHECK-ARMv6-LABEL: load_i32_by_i16_i8:
137; CHECK-ARMv6: ldr r0, [r0]
138; CHECK-ARMv6-NEXT: bx lr
139 %tmp = bitcast i32* %arg to i16*
140 %tmp1 = bitcast i32* %arg to i8*
141 %tmp2 = load i16, i16* %tmp, align 4
142 %tmp3 = zext i16 %tmp2 to i32
143 %tmp4 = shl nuw nsw i32 %tmp3, 16
144 %tmp5 = getelementptr inbounds i8, i8* %tmp1, i32 2
145 %tmp6 = load i8, i8* %tmp5, align 1
146 %tmp7 = zext i8 %tmp6 to i32
147 %tmp8 = shl nuw nsw i32 %tmp7, 8
148 %tmp9 = getelementptr inbounds i8, i8* %tmp1, i32 3
149 %tmp10 = load i8, i8* %tmp9, align 1
150 %tmp11 = zext i8 %tmp10 to i32
151 %tmp12 = or i32 %tmp8, %tmp11
152 %tmp13 = or i32 %tmp12, %tmp4
153 ret i32 %tmp13
154}
155
156; i8* p; // p is 8 byte aligned
157; (i64) p[0] | ((i64) p[1] << 8) | ((i64) p[2] << 16) | ((i64) p[3] << 24) | ((i64) p[4] << 32) | ((i64) p[5] << 40) | ((i64) p[6] << 48) | ((i64) p[7] << 56)
158define i64 @load_i64_by_i8_bswap(i64* %arg) {
159; CHECK-LABEL: load_i64_by_i8_bswap:
160; CHECK: ldr{{.*}}r0
161; CHECK: ldr{{.*}}r0
162; CHECK: and
163; CHECK-NEXT: and
164; CHECK-NEXT: orr
165; CHECK-NEXT: orr
166; CHECK-NEXT: and
167; CHECK-NEXT: orr
168; CHECK-NEXT: and
169; CHECK-NEXT: orr
170; CHECK-NEXT: orr
171; CHECK-NEXT: orr
172; CHECK: mov pc, lr
173
174; CHECK-ARMv6-LABEL: load_i64_by_i8_bswap:
175; CHECK-ARMv6: ldrd r2, r3, [r0]
176; CHECK-ARMv6: rev r0, r3
177; CHECK-ARMv6: rev r1, r2
178; CHECK-ARMv6: bx lr
179 %tmp = bitcast i64* %arg to i8*
180 %tmp1 = load i8, i8* %tmp, align 8
181 %tmp2 = zext i8 %tmp1 to i64
182 %tmp3 = getelementptr inbounds i8, i8* %tmp, i64 1
183 %tmp4 = load i8, i8* %tmp3, align 1
184 %tmp5 = zext i8 %tmp4 to i64
185 %tmp6 = shl nuw nsw i64 %tmp5, 8
186 %tmp7 = or i64 %tmp6, %tmp2
187 %tmp8 = getelementptr inbounds i8, i8* %tmp, i64 2
188 %tmp9 = load i8, i8* %tmp8, align 1
189 %tmp10 = zext i8 %tmp9 to i64
190 %tmp11 = shl nuw nsw i64 %tmp10, 16
191 %tmp12 = or i64 %tmp7, %tmp11
192 %tmp13 = getelementptr inbounds i8, i8* %tmp, i64 3
193 %tmp14 = load i8, i8* %tmp13, align 1
194 %tmp15 = zext i8 %tmp14 to i64
195 %tmp16 = shl nuw nsw i64 %tmp15, 24
196 %tmp17 = or i64 %tmp12, %tmp16
197 %tmp18 = getelementptr inbounds i8, i8* %tmp, i64 4
198 %tmp19 = load i8, i8* %tmp18, align 1
199 %tmp20 = zext i8 %tmp19 to i64
200 %tmp21 = shl nuw nsw i64 %tmp20, 32
201 %tmp22 = or i64 %tmp17, %tmp21
202 %tmp23 = getelementptr inbounds i8, i8* %tmp, i64 5
203 %tmp24 = load i8, i8* %tmp23, align 1
204 %tmp25 = zext i8 %tmp24 to i64
205 %tmp26 = shl nuw nsw i64 %tmp25, 40
206 %tmp27 = or i64 %tmp22, %tmp26
207 %tmp28 = getelementptr inbounds i8, i8* %tmp, i64 6
208 %tmp29 = load i8, i8* %tmp28, align 1
209 %tmp30 = zext i8 %tmp29 to i64
210 %tmp31 = shl nuw nsw i64 %tmp30, 48
211 %tmp32 = or i64 %tmp27, %tmp31
212 %tmp33 = getelementptr inbounds i8, i8* %tmp, i64 7
213 %tmp34 = load i8, i8* %tmp33, align 1
214 %tmp35 = zext i8 %tmp34 to i64
215 %tmp36 = shl nuw i64 %tmp35, 56
216 %tmp37 = or i64 %tmp32, %tmp36
217 ret i64 %tmp37
218}
219
220; i8* p; // p is 8 byte aligned
221; ((i64) p[0] << 56) | ((i64) p[1] << 48) | ((i64) p[2] << 40) | ((i64) p[3] << 32) | ((i64) p[4] << 24) | ((i64) p[5] << 16) | ((i64) p[6] << 8) | (i64) p[7]
222define i64 @load_i64_by_i8(i64* %arg) {
223; CHECK-LABEL: load_i64_by_i8:
224; CHECK: ldr r2, [r0]
225; CHECK: ldr r1, [r0, #4]
226; CHECK: mov r0, r2
227; CHECK: mov pc, lr
228
229; CHECK-ARMv6-LABEL: load_i64_by_i8:
230; CHECK-ARMv6: ldrd r0, r1, [r0]
231; CHECK-ARMv6: bx lr
232 %tmp = bitcast i64* %arg to i8*
233 %tmp1 = load i8, i8* %tmp, align 8
234 %tmp2 = zext i8 %tmp1 to i64
235 %tmp3 = shl nuw i64 %tmp2, 56
236 %tmp4 = getelementptr inbounds i8, i8* %tmp, i64 1
237 %tmp5 = load i8, i8* %tmp4, align 1
238 %tmp6 = zext i8 %tmp5 to i64
239 %tmp7 = shl nuw nsw i64 %tmp6, 48
240 %tmp8 = or i64 %tmp7, %tmp3
241 %tmp9 = getelementptr inbounds i8, i8* %tmp, i64 2
242 %tmp10 = load i8, i8* %tmp9, align 1
243 %tmp11 = zext i8 %tmp10 to i64
244 %tmp12 = shl nuw nsw i64 %tmp11, 40
245 %tmp13 = or i64 %tmp8, %tmp12
246 %tmp14 = getelementptr inbounds i8, i8* %tmp, i64 3
247 %tmp15 = load i8, i8* %tmp14, align 1
248 %tmp16 = zext i8 %tmp15 to i64
249 %tmp17 = shl nuw nsw i64 %tmp16, 32
250 %tmp18 = or i64 %tmp13, %tmp17
251 %tmp19 = getelementptr inbounds i8, i8* %tmp, i64 4
252 %tmp20 = load i8, i8* %tmp19, align 1
253 %tmp21 = zext i8 %tmp20 to i64
254 %tmp22 = shl nuw nsw i64 %tmp21, 24
255 %tmp23 = or i64 %tmp18, %tmp22
256 %tmp24 = getelementptr inbounds i8, i8* %tmp, i64 5
257 %tmp25 = load i8, i8* %tmp24, align 1
258 %tmp26 = zext i8 %tmp25 to i64
259 %tmp27 = shl nuw nsw i64 %tmp26, 16
260 %tmp28 = or i64 %tmp23, %tmp27
261 %tmp29 = getelementptr inbounds i8, i8* %tmp, i64 6
262 %tmp30 = load i8, i8* %tmp29, align 1
263 %tmp31 = zext i8 %tmp30 to i64
264 %tmp32 = shl nuw nsw i64 %tmp31, 8
265 %tmp33 = or i64 %tmp28, %tmp32
266 %tmp34 = getelementptr inbounds i8, i8* %tmp, i64 7
267 %tmp35 = load i8, i8* %tmp34, align 1
268 %tmp36 = zext i8 %tmp35 to i64
269 %tmp37 = or i64 %tmp33, %tmp36
270 ret i64 %tmp37
271}