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gerrit-public.fairphone.software / toolchain / llvm-project / 468487d71ae3641883e06fbc81410d11a146ff02 / . / llvm / lib / Target / X86 / X86MacroFusion.cpp
blob: 9dbe0ecce26f57e43ba43adac6f0a0022fa9db90 [file] [log] [blame]
Evandro Menezes94edf022017-02-01 02:54:34 +0000[diff] [blame]1//===- X86MacroFusion.cpp - X86 Macro Fusion ------------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// \file This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the DAG scheduling mutation to
11// pair instructions back to back.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86MacroFusion.h"
16#include "X86Subtarget.h"
17#include "llvm/Support/CommandLine.h"
18#include "llvm/Target/TargetInstrInfo.h"
19
20#define DEBUG_TYPE "misched"
21
22using namespace llvm;
23
24static cl::opt<bool> EnableMacroFusion("x86-misched-fusion", cl::Hidden,
25 cl::desc("Enable scheduling for macro fusion."), cl::init(true));
26
27namespace {
28
NAKAMURA Takumi468487d2017-02-01 07:30:46 +0000[diff] [blame^]29/// \brief Verify that the instruction pair, First and Second,
Evandro Menezes94edf022017-02-01 02:54:34 +0000[diff] [blame]30/// should be scheduled back to back. If either instruction is unspecified,
31/// then verify that the other instruction may be part of a pair at all.
32static bool shouldScheduleAdjacent(const X86Subtarget &ST,
33 const MachineInstr *First,
34 const MachineInstr *Second) {
35 // Check if this processor supports macro-fusion. Since this is a minor
36 // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
37 // proxy for SandyBridge+.
38 if (!ST.hasAVX())
39 return false;
40
41 enum {
42 FuseTest,
43 FuseCmp,
44 FuseInc
45 } FuseKind;
46
47 unsigned FirstOpcode = First ?
48 First->getOpcode() : X86::INSTRUCTION_LIST_END;
49 unsigned SecondOpcode = Second ?
50 Second->getOpcode() : X86::INSTRUCTION_LIST_END;
51
52 switch (SecondOpcode) {
53 default:
54 return false;
55 case X86::JE_1:
56 case X86::JNE_1:
57 case X86::JL_1:
58 case X86::JLE_1:
59 case X86::JG_1:
60 case X86::JGE_1:
61 FuseKind = FuseInc;
62 break;
63 case X86::JB_1:
64 case X86::JBE_1:
65 case X86::JA_1:
66 case X86::JAE_1:
67 FuseKind = FuseCmp;
68 break;
69 case X86::JS_1:
70 case X86::JNS_1:
71 case X86::JP_1:
72 case X86::JNP_1:
73 case X86::JO_1:
74 case X86::JNO_1:
75 FuseKind = FuseTest;
76 break;
77 }
78
79 switch (FirstOpcode) {
80 default:
81 return false;
82 case X86::TEST8rr:
83 case X86::TEST16rr:
84 case X86::TEST32rr:
85 case X86::TEST64rr:
86 case X86::TEST8ri:
87 case X86::TEST16ri:
88 case X86::TEST32ri:
89 case X86::TEST32i32:
90 case X86::TEST64i32:
91 case X86::TEST64ri32:
92 case X86::TEST8rm:
93 case X86::TEST16rm:
94 case X86::TEST32rm:
95 case X86::TEST64rm:
96 case X86::TEST8ri_NOREX:
97 case X86::AND16i16:
98 case X86::AND16ri:
99 case X86::AND16ri8:
100 case X86::AND16rm:
101 case X86::AND16rr:
102 case X86::AND32i32:
103 case X86::AND32ri:
104 case X86::AND32ri8:
105 case X86::AND32rm:
106 case X86::AND32rr:
107 case X86::AND64i32:
108 case X86::AND64ri32:
109 case X86::AND64ri8:
110 case X86::AND64rm:
111 case X86::AND64rr:
112 case X86::AND8i8:
113 case X86::AND8ri:
114 case X86::AND8rm:
115 case X86::AND8rr:
116 return true;
117 case X86::CMP16i16:
118 case X86::CMP16ri:
119 case X86::CMP16ri8:
120 case X86::CMP16rm:
121 case X86::CMP16rr:
122 case X86::CMP32i32:
123 case X86::CMP32ri:
124 case X86::CMP32ri8:
125 case X86::CMP32rm:
126 case X86::CMP32rr:
127 case X86::CMP64i32:
128 case X86::CMP64ri32:
129 case X86::CMP64ri8:
130 case X86::CMP64rm:
131 case X86::CMP64rr:
132 case X86::CMP8i8:
133 case X86::CMP8ri:
134 case X86::CMP8rm:
135 case X86::CMP8rr:
136 case X86::ADD16i16:
137 case X86::ADD16ri:
138 case X86::ADD16ri8:
139 case X86::ADD16ri8_DB:
140 case X86::ADD16ri_DB:
141 case X86::ADD16rm:
142 case X86::ADD16rr:
143 case X86::ADD16rr_DB:
144 case X86::ADD32i32:
145 case X86::ADD32ri:
146 case X86::ADD32ri8:
147 case X86::ADD32ri8_DB:
148 case X86::ADD32ri_DB:
149 case X86::ADD32rm:
150 case X86::ADD32rr:
151 case X86::ADD32rr_DB:
152 case X86::ADD64i32:
153 case X86::ADD64ri32:
154 case X86::ADD64ri32_DB:
155 case X86::ADD64ri8:
156 case X86::ADD64ri8_DB:
157 case X86::ADD64rm:
158 case X86::ADD64rr:
159 case X86::ADD64rr_DB:
160 case X86::ADD8i8:
161 case X86::ADD8mi:
162 case X86::ADD8mr:
163 case X86::ADD8ri:
164 case X86::ADD8rm:
165 case X86::ADD8rr:
166 case X86::SUB16i16:
167 case X86::SUB16ri:
168 case X86::SUB16ri8:
169 case X86::SUB16rm:
170 case X86::SUB16rr:
171 case X86::SUB32i32:
172 case X86::SUB32ri:
173 case X86::SUB32ri8:
174 case X86::SUB32rm:
175 case X86::SUB32rr:
176 case X86::SUB64i32:
177 case X86::SUB64ri32:
178 case X86::SUB64ri8:
179 case X86::SUB64rm:
180 case X86::SUB64rr:
181 case X86::SUB8i8:
182 case X86::SUB8ri:
183 case X86::SUB8rm:
184 case X86::SUB8rr:
185 return FuseKind == FuseCmp || FuseKind == FuseInc;
186 case X86::INC16r:
187 case X86::INC32r:
188 case X86::INC64r:
189 case X86::INC8r:
190 case X86::DEC16r:
191 case X86::DEC32r:
192 case X86::DEC64r:
193 case X86::DEC8r:
194 return FuseKind == FuseInc;
195 case X86::INSTRUCTION_LIST_END:
196 return true;
197 }
198}
199
200/// \brief Post-process the DAG to create cluster edges between instructions
201/// that may be fused by the processor into a single operation.
202class X86MacroFusion : public ScheduleDAGMutation {
203public:
204 X86MacroFusion() {}
205
206 void apply(ScheduleDAGInstrs *DAGInstrs) override;
207};
208
209void X86MacroFusion::apply(ScheduleDAGInstrs *DAGInstrs) {
210 ScheduleDAGMI *DAG = static_cast<ScheduleDAGMI*>(DAGInstrs);
211 const X86Subtarget &ST = DAG->MF.getSubtarget<X86Subtarget>();
212
213 // For now, assume targets can only fuse with the branch.
214 SUnit &ExitSU = DAG->ExitSU;
215 MachineInstr *Branch = ExitSU.getInstr();
216 if (!shouldScheduleAdjacent(ST, nullptr, Branch))
217 return;
218
219 for (SDep &PredDep : ExitSU.Preds) {
220 if (PredDep.isWeak())
221 continue;
222 SUnit &SU = *PredDep.getSUnit();
223 MachineInstr &Pred = *SU.getInstr();
224 if (!shouldScheduleAdjacent(ST, &Pred, Branch))
225 continue;
226
227 // Create a single weak edge from SU to ExitSU. The only effect is to cause
228 // bottom-up scheduling to heavily prioritize the clustered SU. There is no
229 // need to copy predecessor edges from ExitSU to SU, since top-down
230 // scheduling cannot prioritize ExitSU anyway. To defer top-down scheduling
231 // of SU, we could create an artificial edge from the deepest root, but it
232 // hasn't been needed yet.
233 bool Success = DAG->addEdge(&ExitSU, SDep(&SU, SDep::Cluster));
234 (void)Success;
235 assert(Success && "No DAG nodes should be reachable from ExitSU");
236
237 // Adjust latency of data deps between the nodes.
238 for (SDep &PredDep : ExitSU.Preds)
239 if (PredDep.getSUnit() == &SU)
240 PredDep.setLatency(0);
241 for (SDep &SuccDep : SU.Succs)
242 if (SuccDep.getSUnit() == &ExitSU)
243 SuccDep.setLatency(0);
244
245 DEBUG(dbgs() << "Macro fuse ";
246 SU.print(dbgs(), DAG);
247 dbgs() << " - ExitSU" << '\n');
248
249 break;
250 }
251}
252
253} // end namespace
254
255namespace llvm {
256
257std::unique_ptr<ScheduleDAGMutation>
258createX86MacroFusionDAGMutation () {
259 return EnableMacroFusion ? make_unique<X86MacroFusion>() : nullptr;
260}
261
262} // end namespace llvm