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Ulrich Weigand9e3577f2013-05-06 16:17:29 +00001; Test 64-bit comparisons in which the second operand is sign-extended
2; from a PC-relative i32.
3;
4; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
5
6@g = global i32 1
Richard Sandiford46af5a22013-05-30 09:45:42 +00007@h = global i32 1, align 2, section "foo"
Ulrich Weigand9e3577f2013-05-06 16:17:29 +00008
9; Check signed comparison.
10define i64 @f1(i64 %src1) {
11; CHECK: f1:
12; CHECK: cgfrl %r2, g
Richard Sandiford586f4172013-05-21 08:53:17 +000013; CHECK-NEXT: jl
Ulrich Weigand9e3577f2013-05-06 16:17:29 +000014; CHECK: br %r14
15entry:
16 %val = load i32 *@g
17 %src2 = sext i32 %val to i64
18 %cond = icmp slt i64 %src1, %src2
19 br i1 %cond, label %exit, label %mulb
20mulb:
21 %mul = mul i64 %src1, %src1
22 br label %exit
23exit:
24 %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
25 ret i64 %res
26}
27
28; Check unsigned comparison, which cannot use CHRL.
29define i64 @f2(i64 %src1) {
30; CHECK: f2:
31; CHECK-NOT: cgfrl
32; CHECK: br %r14
33entry:
34 %val = load i32 *@g
35 %src2 = sext i32 %val to i64
36 %cond = icmp ult i64 %src1, %src2
37 br i1 %cond, label %exit, label %mulb
38mulb:
39 %mul = mul i64 %src1, %src1
40 br label %exit
41exit:
42 %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
43 ret i64 %res
44}
45
46; Check equality.
47define i64 @f3(i64 %src1) {
48; CHECK: f3:
49; CHECK: cgfrl %r2, g
Richard Sandiford586f4172013-05-21 08:53:17 +000050; CHECK-NEXT: je
Ulrich Weigand9e3577f2013-05-06 16:17:29 +000051; CHECK: br %r14
52entry:
53 %val = load i32 *@g
54 %src2 = sext i32 %val to i64
55 %cond = icmp eq i64 %src1, %src2
56 br i1 %cond, label %exit, label %mulb
57mulb:
58 %mul = mul i64 %src1, %src1
59 br label %exit
60exit:
61 %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
62 ret i64 %res
63}
64
65; Check inequality.
66define i64 @f4(i64 %src1) {
67; CHECK: f4:
68; CHECK: cgfrl %r2, g
Richard Sandiford586f4172013-05-21 08:53:17 +000069; CHECK-NEXT: jlh
Ulrich Weigand9e3577f2013-05-06 16:17:29 +000070; CHECK: br %r14
71entry:
72 %val = load i32 *@g
73 %src2 = sext i32 %val to i64
74 %cond = icmp ne i64 %src1, %src2
75 br i1 %cond, label %exit, label %mulb
76mulb:
77 %mul = mul i64 %src1, %src1
78 br label %exit
79exit:
80 %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
81 ret i64 %res
82}
Richard Sandiford46af5a22013-05-30 09:45:42 +000083
84; Repeat f1 with an unaligned address.
85define i64 @f5(i64 %src1) {
86; CHECK: f5:
87; CHECK: larl [[REG:%r[0-5]]], h
88; CHECK: cgf %r2, 0([[REG]])
89; CHECK-NEXT: jl
90; CHECK: br %r14
91entry:
92 %val = load i32 *@h, align 2
93 %src2 = sext i32 %val to i64
94 %cond = icmp slt i64 %src1, %src2
95 br i1 %cond, label %exit, label %mulb
96mulb:
97 %mul = mul i64 %src1, %src1
98 br label %exit
99exit:
100 %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
101 ret i64 %res
102}