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Ulrich Weigand9e3577f2013-05-06 16:17:29 +00001; Test 64-bit comparisons in which the second operand is a PC-relative
2; variable.
3;
4; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
5
6@g = global i64 1
Richard Sandiford46af5a22013-05-30 09:45:42 +00007@h = global i64 1, align 4, section "foo"
Ulrich Weigand9e3577f2013-05-06 16:17:29 +00008
9; Check signed comparisons.
10define i64 @f1(i64 %src1) {
11; CHECK: f1:
12; CHECK: cgrl %r2, g
Richard Sandiford586f4172013-05-21 08:53:17 +000013; CHECK-NEXT: jl
Ulrich Weigand9e3577f2013-05-06 16:17:29 +000014; CHECK: br %r14
15entry:
16 %src2 = load i64 *@g
17 %cond = icmp slt i64 %src1, %src2
18 br i1 %cond, label %exit, label %mulb
19mulb:
20 %mul = mul i64 %src1, %src1
21 br label %exit
22exit:
23 %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
24 ret i64 %res
25}
26
27; Check unsigned comparisons.
28define i64 @f2(i64 %src1) {
29; CHECK: f2:
30; CHECK: clgrl %r2, g
Richard Sandiford586f4172013-05-21 08:53:17 +000031; CHECK-NEXT: jl
Ulrich Weigand9e3577f2013-05-06 16:17:29 +000032; CHECK: br %r14
33entry:
34 %src2 = load i64 *@g
35 %cond = icmp ult i64 %src1, %src2
36 br i1 %cond, label %exit, label %mulb
37mulb:
38 %mul = mul i64 %src1, %src1
39 br label %exit
40exit:
41 %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
42 ret i64 %res
43}
44
45; Check equality, which can use CRL or CLRL.
46define i64 @f3(i64 %src1) {
47; CHECK: f3:
48; CHECK: c{{l?}}grl %r2, g
Richard Sandiford586f4172013-05-21 08:53:17 +000049; CHECK-NEXT: je
Ulrich Weigand9e3577f2013-05-06 16:17:29 +000050; CHECK: br %r14
51entry:
52 %src2 = load i64 *@g
53 %cond = icmp eq i64 %src1, %src2
54 br i1 %cond, label %exit, label %mulb
55mulb:
56 %mul = mul i64 %src1, %src1
57 br label %exit
58exit:
59 %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
60 ret i64 %res
61}
62
63; ...likewise inequality.
64define i64 @f4(i64 %src1) {
65; CHECK: f4:
66; CHECK: c{{l?}}grl %r2, g
Richard Sandiford586f4172013-05-21 08:53:17 +000067; CHECK-NEXT: jlh
Ulrich Weigand9e3577f2013-05-06 16:17:29 +000068; CHECK: br %r14
69entry:
70 %src2 = load i64 *@g
71 %cond = icmp ne i64 %src1, %src2
72 br i1 %cond, label %exit, label %mulb
73mulb:
74 %mul = mul i64 %src1, %src1
75 br label %exit
76exit:
77 %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
78 ret i64 %res
79}
Richard Sandiford46af5a22013-05-30 09:45:42 +000080
81; Repeat f1 with an unaligned address.
82define i64 @f5(i64 %src1) {
83; CHECK: f5:
84; CHECK: larl [[REG:%r[0-5]]], h
85; CHECK: cg %r2, 0([[REG]])
86; CHECK-NEXT: jl
87; CHECK: br %r14
88entry:
89 %src2 = load i64 *@h, align 4
90 %cond = icmp slt i64 %src1, %src2
91 br i1 %cond, label %exit, label %mulb
92mulb:
93 %mul = mul i64 %src1, %src1
94 br label %exit
95exit:
96 %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
97 ret i64 %res
98}