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Tom Stellardcb97e3a2013-04-15 17:51:35 +00001//===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8/// \file
9//===----------------------------------------------------------------------===//
10
Benjamin Kramera7c40ef2014-08-13 16:26:38 +000011#ifndef LLVM_LIB_TARGET_R600_SIDEFINES_H
12#define LLVM_LIB_TARGET_R600_SIDEFINES_H
Tom Stellardcb97e3a2013-04-15 17:51:35 +000013
Tom Stellard16a9a202013-08-14 23:24:17 +000014namespace SIInstrFlags {
Matt Arsenaulte2fabd32014-07-29 18:51:56 +000015// This needs to be kept in sync with the field bits in InstSI.
Tom Stellard16a9a202013-08-14 23:24:17 +000016enum {
Matt Arsenaultc5f174d2014-12-01 15:52:46 +000017 SALU = 1 << 3,
18 VALU = 1 << 4,
19
20 SOP1 = 1 << 5,
21 SOP2 = 1 << 6,
22 SOPC = 1 << 7,
23 SOPK = 1 << 8,
24 SOPP = 1 << 9,
25
26 VOP1 = 1 << 10,
27 VOP2 = 1 << 11,
28 VOP3 = 1 << 12,
29 VOPC = 1 << 13,
30
31 MUBUF = 1 << 14,
32 MTBUF = 1 << 15,
33 SMRD = 1 << 16,
34 DS = 1 << 17,
35 MIMG = 1 << 18,
36 FLAT = 1 << 19
Tom Stellard16a9a202013-08-14 23:24:17 +000037};
38}
39
Matt Arsenault9783e002014-09-29 15:50:26 +000040namespace SIInstrFlags {
41 enum Flags {
42 // First 4 bits are the instruction encoding
43 VM_CNT = 1 << 0,
44 EXP_CNT = 1 << 1,
45 LGKM_CNT = 1 << 2
46 };
Matt Arsenault4831ce52015-01-06 23:00:37 +000047
48 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
49 // The result is true if any of these tests are true.
50 enum ClassFlags {
51 S_NAN = 1 << 0, // Signaling NaN
52 Q_NAN = 1 << 1, // Quiet NaN
53 N_INFINITY = 1 << 2, // Negative infinity
54 N_NORMAL = 1 << 3, // Negative normal
55 N_SUBNORMAL = 1 << 4, // Negative subnormal
56 N_ZERO = 1 << 5, // Negative zero
57 P_ZERO = 1 << 6, // Positive zero
58 P_SUBNORMAL = 1 << 7, // Positive subnormal
59 P_NORMAL = 1 << 8, // Positive normal
60 P_INFINITY = 1 << 9 // Positive infinity
61 };
Matt Arsenault9783e002014-09-29 15:50:26 +000062}
63
64namespace SISrcMods {
65 enum {
66 NEG = 1 << 0,
67 ABS = 1 << 1
68 };
69}
70
Matt Arsenault97069782014-09-30 19:49:48 +000071namespace SIOutMods {
72 enum {
73 NONE = 0,
74 MUL2 = 1,
75 MUL4 = 2,
76 DIV2 = 3
77 };
78}
79
Tom Stellardcb97e3a2013-04-15 17:51:35 +000080#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
Michel Danzer49812b52013-07-10 16:37:07 +000081#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
82#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
Tom Stellardcb97e3a2013-04-15 17:51:35 +000083#define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
84#define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
85#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
86#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
87#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
Michel Danzer49812b52013-07-10 16:37:07 +000088#define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
Tom Stellard4df465b2014-12-02 21:28:53 +000089#define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
90#define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
91#define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
92#define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
93#define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
94#define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
95#define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
96
Michel Danzer49812b52013-07-10 16:37:07 +000097#define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
Tom Stellardcb97e3a2013-04-15 17:51:35 +000098#define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
99
Matt Arsenault0989d512014-06-26 17:22:30 +0000100
101#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
102#define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
103#define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
104#define C_00B848_VGPRS 0xFFFFFFC0
105#define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
106#define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
107#define C_00B848_SGPRS 0xFFFFFC3F
108#define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
109#define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
110#define C_00B848_PRIORITY 0xFFFFF3FF
111#define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
112#define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
113#define C_00B848_FLOAT_MODE 0xFFF00FFF
114#define S_00B848_PRIV(x) (((x) & 0x1) << 20)
115#define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
116#define C_00B848_PRIV 0xFFEFFFFF
117#define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
118#define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
119#define C_00B848_DX10_CLAMP 0xFFDFFFFF
120#define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
121#define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
122#define C_00B848_DEBUG_MODE 0xFFBFFFFF
123#define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
124#define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
125#define C_00B848_IEEE_MODE 0xFF7FFFFF
126
127
128// Helpers for setting FLOAT_MODE
129#define FP_ROUND_ROUND_TO_NEAREST 0
130#define FP_ROUND_ROUND_TO_INF 1
131#define FP_ROUND_ROUND_TO_NEGINF 2
132#define FP_ROUND_ROUND_TO_ZERO 3
133
134// Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
135// precision.
136#define FP_ROUND_MODE_SP(x) ((x) & 0x3)
137#define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
138
139#define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
140#define FP_DENORM_FLUSH_OUT 1
141#define FP_DENORM_FLUSH_IN 2
142#define FP_DENORM_FLUSH_NONE 3
143
144
145// Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
146// precision.
147#define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
148#define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
149
Tom Stellardb02094e2014-07-21 15:45:01 +0000150#define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
151#define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12)
152
Benjamin Kramera7c40ef2014-08-13 16:26:38 +0000153#endif