blob: 7f5bca8b601b83d46134764eefb8a58bda4c1196 [file] [log] [blame]
Christof Douma4a025cc2018-03-23 13:02:03 +00001; RUN: llc -mtriple=thumbv7m-arm-none-eabi -mattr=+execute-only,+fp-armv8 %s -o - | FileCheck %s
2
3; This function used to run into a code selection error on fp-armv8 due to
4; different ordering of the constant arguments of fcmp. Fixed by extending the
5; code selection to handle the missing case.
6define arm_aapcs_vfpcc void @foo0() local_unnamed_addr {
7 br i1 undef, label %.end, label %1
8
9 %2 = fcmp nsz olt float undef, 0.000000e+00
10 %3 = select i1 %2, float -5.000000e-01, float 5.000000e-01
11 %4 = fadd nsz float undef, %3
12 %5 = fptosi float %4 to i32
13 %6 = ashr i32 %5, 4
14 %7 = icmp slt i32 %6, 0
15 br i1 %7, label %8, label %.end
16
17 tail call arm_aapcs_vfpcc void @bar()
18 br label %.end
19
20.end:
21 ret void
22}
23; CHECK-LABEL: foo0
24; CHECK: vcmpe.f32 {{s[0-9]+}}, #0
25
26
27define arm_aapcs_vfpcc void @float1() local_unnamed_addr {
28 br i1 undef, label %.end, label %1
29
30 %2 = fcmp nsz olt float undef, 1.000000e+00
31 %3 = select i1 %2, float -5.000000e-01, float 5.000000e-01
32 %4 = fadd nsz float undef, %3
33 %5 = fptosi float %4 to i32
34 %6 = ashr i32 %5, 4
35 %7 = icmp slt i32 %6, 0
36 br i1 %7, label %8, label %.end
37
38 tail call arm_aapcs_vfpcc void @bar()
39 br label %.end
40
41.end:
42 ret void
43}
44; CHECK-LABEL: float1
45; CHECK: vmov.f32 [[FPREG:s[0-9]+]], #1.000000e+00
46; CHECK: vcmpe.f32 [[FPREG]], {{s[0-9]+}}
47
48define arm_aapcs_vfpcc void @float128() local_unnamed_addr {
49 br i1 undef, label %.end, label %1
50
51 %2 = fcmp nsz olt float undef, 128.000000e+00
52 %3 = select i1 %2, float -5.000000e-01, float 5.000000e-01
53 %4 = fadd nsz float undef, %3
54 %5 = fptosi float %4 to i32
55 %6 = ashr i32 %5, 4
56 %7 = icmp slt i32 %6, 0
57 br i1 %7, label %8, label %.end
58
59 tail call arm_aapcs_vfpcc void @bar()
60 br label %.end
61
62.end:
63 ret void
64}
65; CHECK-LABEL: float128
66; CHECK: mov.w [[REG:r[0-9]+]], #1124073472
67; CHECK: vmov [[FPREG:s[0-9]+]], [[REG]]
68; CHECK: vcmpe.f32 [[FPREG]], {{s[0-9]+}}
69
70
71define arm_aapcs_vfpcc void @double1() local_unnamed_addr {
72 br i1 undef, label %.end, label %1
73
74 %2 = fcmp nsz olt double undef, 1.000000e+00
75 %3 = select i1 %2, double -5.000000e-01, double 5.000000e-01
76 %4 = fadd nsz double undef, %3
77 %5 = fptosi double %4 to i32
78 %6 = ashr i32 %5, 4
79 %7 = icmp slt i32 %6, 0
80 br i1 %7, label %8, label %.end
81
82 tail call arm_aapcs_vfpcc void @bar()
83 br label %.end
84
85.end:
86 ret void
87}
88; CHECK-LABEL: double1
89; CHECK: vmov.f64 [[FPREG:d[0-9]+]], #1.000000e+00
90; CHECK: vcmpe.f64 [[FPREG]], {{d[0-9]+}}
91
92define arm_aapcs_vfpcc void @double128() local_unnamed_addr {
93 br i1 undef, label %.end, label %1
94
95 %2 = fcmp nsz olt double undef, 128.000000e+00
96 %3 = select i1 %2, double -5.000000e-01, double 5.000000e-01
97 %4 = fadd nsz double undef, %3
98 %5 = fptosi double %4 to i32
99 %6 = ashr i32 %5, 4
100 %7 = icmp slt i32 %6, 0
101 br i1 %7, label %8, label %.end
102
103 tail call arm_aapcs_vfpcc void @bar()
104 br label %.end
105
106.end:
107 ret void
108}
109; CHECK-LABEL: double128
110; CHECK: movs [[REGL:r[0-9]+]], #0
111; CHECK: movs [[REGH:r[0-9]+]], #0
112; CHECK: movt [[REGH]], #16480
113; CHECK: vmov [[FPREG:d[0-9]+]], [[REGL]], [[REGH]]
114; CHECK: vcmpe.f64 [[FPREG]], {{d[0-9]+}}
115
116
117declare arm_aapcs_vfpcc void @bar() local_unnamed_addr
118