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Tim Northover3b0846e2014-05-24 12:50:23 +00001//===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file provides AArch64 specific target descriptions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "AArch64MCTargetDesc.h"
15#include "AArch64ELFStreamer.h"
16#include "AArch64MCAsmInfo.h"
17#include "InstPrinter/AArch64InstPrinter.h"
18#include "llvm/MC/MCCodeGenInfo.h"
19#include "llvm/MC/MCInstrInfo.h"
20#include "llvm/MC/MCRegisterInfo.h"
21#include "llvm/MC/MCStreamer.h"
22#include "llvm/MC/MCSubtargetInfo.h"
23#include "llvm/Support/ErrorHandling.h"
24#include "llvm/Support/TargetRegistry.h"
25
26using namespace llvm;
27
28#define GET_INSTRINFO_MC_DESC
29#include "AArch64GenInstrInfo.inc"
30
31#define GET_SUBTARGETINFO_MC_DESC
32#include "AArch64GenSubtargetInfo.inc"
33
34#define GET_REGINFO_MC_DESC
35#include "AArch64GenRegisterInfo.inc"
36
37static MCInstrInfo *createAArch64MCInstrInfo() {
38 MCInstrInfo *X = new MCInstrInfo();
39 InitAArch64MCInstrInfo(X);
40 return X;
41}
42
43static MCSubtargetInfo *
44createAArch64MCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) {
45 MCSubtargetInfo *X = new MCSubtargetInfo();
46
47 if (CPU.empty())
48 CPU = "generic";
49
50 InitAArch64MCSubtargetInfo(X, TT, CPU, FS);
51 return X;
52}
53
54static MCRegisterInfo *createAArch64MCRegisterInfo(StringRef Triple) {
55 MCRegisterInfo *X = new MCRegisterInfo();
56 InitAArch64MCRegisterInfo(X, AArch64::LR);
57 return X;
58}
59
60static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI,
61 StringRef TT) {
62 Triple TheTriple(TT);
63
64 MCAsmInfo *MAI;
65 if (TheTriple.isOSDarwin())
66 MAI = new AArch64MCAsmInfoDarwin();
67 else {
68 assert(TheTriple.isOSBinFormatELF() && "Only expect Darwin or ELF");
69 MAI = new AArch64MCAsmInfoELF(TT);
70 }
71
72 // Initial state of the frame pointer is SP.
73 unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true);
74 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
75 MAI->addInitialFrameState(Inst);
76
77 return MAI;
78}
79
80static MCCodeGenInfo *createAArch64MCCodeGenInfo(StringRef TT, Reloc::Model RM,
81 CodeModel::Model CM,
82 CodeGenOpt::Level OL) {
83 Triple TheTriple(TT);
84 assert((TheTriple.isOSBinFormatELF() || TheTriple.isOSBinFormatMachO()) &&
85 "Only expect Darwin and ELF targets");
86
87 if (CM == CodeModel::Default)
88 CM = CodeModel::Small;
89 // The default MCJIT memory managers make no guarantees about where they can
90 // find an executable page; JITed code needs to be able to refer to globals
91 // no matter how far away they are.
92 else if (CM == CodeModel::JITDefault)
93 CM = CodeModel::Large;
94 else if (CM != CodeModel::Small && CM != CodeModel::Large)
95 report_fatal_error(
96 "Only small and large code models are allowed on AArch64");
97
98 // AArch64 Darwin is always PIC.
99 if (TheTriple.isOSDarwin())
100 RM = Reloc::PIC_;
101 // On ELF platforms the default static relocation model has a smart enough
102 // linker to cope with referencing external symbols defined in a shared
103 // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
104 else if (RM == Reloc::Default || RM == Reloc::DynamicNoPIC)
105 RM = Reloc::Static;
106
107 MCCodeGenInfo *X = new MCCodeGenInfo();
Jim Grosbach4c98cf72015-05-15 19:13:31 +0000108 X->initMCCodeGenInfo(RM, CM, OL);
Tim Northover3b0846e2014-05-24 12:50:23 +0000109 return X;
110}
111
Eric Christopherf8019402015-03-31 00:10:04 +0000112static MCInstPrinter *createAArch64MCInstPrinter(const Triple &T,
113 unsigned SyntaxVariant,
Tim Northover3b0846e2014-05-24 12:50:23 +0000114 const MCAsmInfo &MAI,
115 const MCInstrInfo &MII,
Eric Christopherf8019402015-03-31 00:10:04 +0000116 const MCRegisterInfo &MRI) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000117 if (SyntaxVariant == 0)
Eric Christopher2226c722015-03-30 21:52:26 +0000118 return new AArch64InstPrinter(MAI, MII, MRI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000119 if (SyntaxVariant == 1)
Eric Christopher2226c722015-03-30 21:52:26 +0000120 return new AArch64AppleInstPrinter(MAI, MII, MRI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000121
122 return nullptr;
123}
124
Rafael Espindolacd584a82015-03-19 01:50:16 +0000125static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
Rafael Espindola5560a4c2015-04-14 22:14:34 +0000126 MCAsmBackend &TAB, raw_pwrite_stream &OS,
Rafael Espindolacd584a82015-03-19 01:50:16 +0000127 MCCodeEmitter *Emitter, bool RelaxAll) {
Rafael Espindola7b61ddf2014-10-15 16:12:52 +0000128 return createAArch64ELFStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
Tim Northover3b0846e2014-05-24 12:50:23 +0000129}
130
Rafael Espindolacd584a82015-03-19 01:50:16 +0000131static MCStreamer *createMachOStreamer(MCContext &Ctx, MCAsmBackend &TAB,
Rafael Espindola5560a4c2015-04-14 22:14:34 +0000132 raw_pwrite_stream &OS,
133 MCCodeEmitter *Emitter, bool RelaxAll,
Rafael Espindola36a15cb2015-03-20 20:00:01 +0000134 bool DWARFMustBeAtTheEnd) {
Rafael Espindolacd584a82015-03-19 01:50:16 +0000135 return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll,
Rafael Espindola36a15cb2015-03-20 20:00:01 +0000136 DWARFMustBeAtTheEnd,
Rafael Espindolacd584a82015-03-19 01:50:16 +0000137 /*LabelSections*/ true);
138}
139
Tim Northover3b0846e2014-05-24 12:50:23 +0000140// Force static initialization.
141extern "C" void LLVMInitializeAArch64TargetMC() {
Rafael Espindola69244c32015-03-18 23:15:49 +0000142 for (Target *T :
143 {&TheAArch64leTarget, &TheAArch64beTarget, &TheARM64Target}) {
144 // Register the MC asm info.
145 RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo);
Tim Northover3b0846e2014-05-24 12:50:23 +0000146
Rafael Espindola69244c32015-03-18 23:15:49 +0000147 // Register the MC codegen info.
148 TargetRegistry::RegisterMCCodeGenInfo(*T, createAArch64MCCodeGenInfo);
Tim Northover3b0846e2014-05-24 12:50:23 +0000149
Rafael Espindola69244c32015-03-18 23:15:49 +0000150 // Register the MC instruction info.
151 TargetRegistry::RegisterMCInstrInfo(*T, createAArch64MCInstrInfo);
Tim Northover3b0846e2014-05-24 12:50:23 +0000152
Rafael Espindola69244c32015-03-18 23:15:49 +0000153 // Register the MC register info.
154 TargetRegistry::RegisterMCRegInfo(*T, createAArch64MCRegisterInfo);
Tim Northover3b0846e2014-05-24 12:50:23 +0000155
Rafael Espindola69244c32015-03-18 23:15:49 +0000156 // Register the MC subtarget info.
157 TargetRegistry::RegisterMCSubtargetInfo(*T, createAArch64MCSubtargetInfo);
158
159 // Register the MC Code Emitter
160 TargetRegistry::RegisterMCCodeEmitter(*T, createAArch64MCCodeEmitter);
161
Rafael Espindolacd584a82015-03-19 01:50:16 +0000162 // Register the obj streamers.
163 TargetRegistry::RegisterELFStreamer(*T, createELFStreamer);
164 TargetRegistry::RegisterMachOStreamer(*T, createMachOStreamer);
165
166 // Register the obj target streamer.
167 TargetRegistry::RegisterObjectTargetStreamer(
168 *T, createAArch64ObjectTargetStreamer);
Rafael Espindola69244c32015-03-18 23:15:49 +0000169
170 // Register the asm streamer.
171 TargetRegistry::RegisterAsmTargetStreamer(*T,
172 createAArch64AsmTargetStreamer);
173 // Register the MCInstPrinter.
174 TargetRegistry::RegisterMCInstPrinter(*T, createAArch64MCInstPrinter);
175 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000176
177 // Register the asm backend.
Rafael Espindola69244c32015-03-18 23:15:49 +0000178 for (Target *T : {&TheAArch64leTarget, &TheARM64Target})
179 TargetRegistry::RegisterMCAsmBackend(*T, createAArch64leAsmBackend);
Tim Northover3b0846e2014-05-24 12:50:23 +0000180 TargetRegistry::RegisterMCAsmBackend(TheAArch64beTarget,
181 createAArch64beAsmBackend);
Tim Northover3b0846e2014-05-24 12:50:23 +0000182}