| NAKAMURA Takumi | 4cf1a3b | 2014-03-30 05:01:04 +0000 | [diff] [blame^] | 1 | ; RUN: llc -mtriple=arm64-unknown-unknown -mcpu=cyclone -pre-RA-sched=list-hybrid < %s | FileCheck %s |
| Tim Northover | 00ed996 | 2014-03-29 10:18:08 +0000 | [diff] [blame] | 2 | ; rdar://10232252 |
| 3 | ; Prevent LSR of doing poor choice that cannot be folded in addressing mode |
| 4 | |
| 5 | ; Remove the -pre-RA-sched=list-hybrid option after fixing: |
| 6 | ; <rdar://problem/12702735> [ARM64][coalescer] need better register |
| 7 | ; coalescing for simple unit tests. |
| 8 | |
| 9 | ; CHECK: testCase |
| 10 | ; CHECK: %while.body{{$}} |
| 11 | ; CHECK: ldr [[STREG:x[0-9]+]], [{{x[0-9]+}}], #8 |
| 12 | ; CHECK-NEXT: str [[STREG]], [{{x[0-9]+}}], #8 |
| 13 | ; CHECK: %while.end |
| 14 | define i32 @testCase() nounwind ssp { |
| 15 | entry: |
| 16 | br label %while.body |
| 17 | |
| 18 | while.body: ; preds = %while.body, %entry |
| 19 | %len.06 = phi i64 [ 1288, %entry ], [ %sub, %while.body ] |
| 20 | %pDst.05 = phi i64* [ inttoptr (i64 6442450944 to i64*), %entry ], [ %incdec.ptr1, %while.body ] |
| 21 | %pSrc.04 = phi i64* [ inttoptr (i64 4294967296 to i64*), %entry ], [ %incdec.ptr, %while.body ] |
| 22 | %incdec.ptr = getelementptr inbounds i64* %pSrc.04, i64 1 |
| 23 | %tmp = load volatile i64* %pSrc.04, align 8 |
| 24 | %incdec.ptr1 = getelementptr inbounds i64* %pDst.05, i64 1 |
| 25 | store volatile i64 %tmp, i64* %pDst.05, align 8 |
| 26 | %sub = add i64 %len.06, -8 |
| 27 | %cmp = icmp sgt i64 %sub, -1 |
| 28 | br i1 %cmp, label %while.body, label %while.end |
| 29 | |
| 30 | while.end: ; preds = %while.body |
| 31 | tail call void inttoptr (i64 6442450944 to void ()*)() nounwind |
| 32 | ret i32 0 |
| 33 | } |