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gerrit-public.fairphone.software / toolchain / llvm-project / 501977eb7ae8cded22fb85330c6e6fab19b52b25 / . / llvm / test / CodeGen / ARM / a15-SD-dep.ll
blob: 019ff6129b0072550ec8626f5893247fd015d0bc [file] [log] [blame]
Tim Northover501977e2013-08-12 12:43:26 +0000[diff] [blame^]1; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -disable-a15-sd-optimization -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK-DISABLED %s
2; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK-ENABLED %s
Silviu Baranga82dd6ac2013-03-15 18:28:25 +0000[diff] [blame]3
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]4; CHECK-ENABLED-LABEL: t1:
5; CHECK-DISABLED-LABEL: t1:
Silviu Baranga82dd6ac2013-03-15 18:28:25 +0000[diff] [blame]6define <2 x float> @t1(float %f) {
7 ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0]
Silviu Barangadc453362013-03-27 12:38:44 +0000[diff] [blame]8 ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0]
Silviu Baranga82dd6ac2013-03-15 18:28:25 +0000[diff] [blame]9 %i1 = insertelement <2 x float> undef, float %f, i32 1
10 %i2 = fadd <2 x float> %i1, %i1
11 ret <2 x float> %i2
12}
13
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]14; CHECK-ENABLED-LABEL: t2:
15; CHECK-DISABLED-LABEL: t2:
Silviu Baranga82dd6ac2013-03-15 18:28:25 +0000[diff] [blame]16define <4 x float> @t2(float %g, float %f) {
17 ; CHECK-ENABLED: vdup.32 q{{[0-9]*}}, d0[0]
Silviu Barangadc453362013-03-27 12:38:44 +0000[diff] [blame]18 ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0]
Silviu Baranga82dd6ac2013-03-15 18:28:25 +0000[diff] [blame]19 %i1 = insertelement <4 x float> undef, float %f, i32 1
20 %i2 = fadd <4 x float> %i1, %i1
21 ret <4 x float> %i2
22}
23
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]24; CHECK-ENABLED-LABEL: t3:
25; CHECK-DISABLED-LABEL: t3:
Silviu Baranga82dd6ac2013-03-15 18:28:25 +0000[diff] [blame]26define arm_aapcs_vfpcc <2 x float> @t3(float %f) {
27 ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0]
Silviu Barangadc453362013-03-27 12:38:44 +0000[diff] [blame]28 ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0]
Silviu Baranga82dd6ac2013-03-15 18:28:25 +0000[diff] [blame]29 %i1 = insertelement <2 x float> undef, float %f, i32 1
30 %i2 = fadd <2 x float> %i1, %i1
31 ret <2 x float> %i2
32}
33
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]34; CHECK-ENABLED-LABEL: t4:
35; CHECK-DISABLED-LABEL: t4:
Silviu Baranga82dd6ac2013-03-15 18:28:25 +0000[diff] [blame]36define <2 x float> @t4(float %f) {
37 ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0]
38 ; CHECK-DISABLED-NOT: vdup
39 %i1 = insertelement <2 x float> undef, float %f, i32 1
40 br label %b
41
42 ; Block %b has an S-reg as live-in.
43b:
44 %i2 = fadd <2 x float> %i1, %i1
45 ret <2 x float> %i2
46}
47
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]48; CHECK-ENABLED-LABEL: t5:
49; CHECK-DISABLED-LABEL: t5:
Silviu Baranga82dd6ac2013-03-15 18:28:25 +0000[diff] [blame]50define arm_aapcs_vfpcc <4 x float> @t5(<4 x float> %q, float %f) {
51 ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d{{[0-9]*}}[0]
52 ; CHECK-ENABLED: vadd.f32
53 ; CHECK-ENABLED-NEXT: bx lr
54 ; CHECK-DISABLED-NOT: vdup
55 %i1 = insertelement <4 x float> %q, float %f, i32 1
56 %i2 = fadd <4 x float> %i1, %i1
57 ret <4 x float> %i2
58}