| Zoran Jovanovic | 2e386d3 | 2015-10-12 16:07:25 +0000 | [diff] [blame] | 1 | //===- MicroMipsDSPInstrInfo.td - Micromips DSP instructions -*- tablegen *-=// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file describes MicroMips DSP instructions. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | // Instruction encoding. |
| Zlatko Buljan | 5292083 | 2015-10-19 07:16:26 +0000 | [diff] [blame^] | 15 | class ADDQ_PH_MM_ENC : POOL32A_3R_FMT<"addq.ph", 0b00000001101>; |
| 16 | class ADDQ_S_PH_MM_ENC : POOL32A_3R_FMT<"addq_s.ph", 0b10000001101>; |
| 17 | class ADDQ_S_W_MM_ENC : POOL32A_3RB0_FMT<"addq_s.w", 0b1100000101>; |
| 18 | class ADDQH_PH_MMR2_ENC : POOL32A_3R_FMT<"addqh.ph", 0b00001001101>; |
| 19 | class ADDQH_R_PH_MMR2_ENC : POOL32A_3R_FMT<"addqh_r.ph", 0b10001001101>; |
| 20 | class ADDQH_W_MMR2_ENC: POOL32A_3R_FMT<"addqh.w", 0b00010001101>; |
| 21 | class ADDQH_R_W_MMR2_ENC : POOL32A_3R_FMT<"addqh_r.w", 0b10010001101>; |
| 22 | class ADDU_PH_MMR2_ENC : POOL32A_3R_FMT<"addu.ph", 0b00100001101>; |
| 23 | class ADDU_S_PH_MMR2_ENC : POOL32A_3R_FMT<"addu_s.ph", 0b10100001101>; |
| Zlatko Buljan | 54b1eb4 | 2015-10-15 08:59:45 +0000 | [diff] [blame] | 24 | class ADDU_QB_MM_ENC : POOL32A_3R_FMT<"addu.qb", 0b00011001101>; |
| Zlatko Buljan | 5292083 | 2015-10-19 07:16:26 +0000 | [diff] [blame^] | 25 | class ADDU_S_QB_MM_ENC : POOL32A_3R_FMT<"addu_s.qb", 0b10011001101>; |
| 26 | class ADDUH_QB_MMR2_ENC : POOL32A_3R_FMT<"adduh.qb", 0b00101001101>; |
| 27 | class ADDUH_R_QB_MMR2_ENC : POOL32A_3R_FMT<"adduh_r.qb", 0b10101001101>; |
| 28 | class ADDSC_MM_ENC : POOL32A_3RB0_FMT<"addsc", 0b1110000101>; |
| 29 | class ADDWC_MM_ENC : POOL32A_3RB0_FMT<"addwc", 0b1111000101>; |
| Zlatko Buljan | 54b1eb4 | 2015-10-15 08:59:45 +0000 | [diff] [blame] | 30 | class DPA_W_PH_MMR2_ENC : POOL32A_AC2R_FMT<"dpa.w.ph", 0b00000010>; |
| 31 | class DPAQ_S_W_PH_MM_ENC : POOL32A_AC2R_FMT<"dpaq_s.w.ph", 0b00001010>; |
| 32 | class DPAQ_SA_L_W_MM_ENC : POOL32A_AC2R_FMT<"dpaq_sa.l.w", 0b01001010>; |
| 33 | class DPAQX_S_W_PH_MMR2_ENC : POOL32A_AC2R_FMT<"dpaqx_s.w.ph", 0b10001010>; |
| 34 | class DPAQX_SA_W_PH_MMR2_ENC : POOL32A_AC2R_FMT<"dpaqx_sa.w.ph", 0b11001010>; |
| 35 | class DPAU_H_QBL_MM_ENC : POOL32A_AC2R_FMT<"dpau.h.qbl", 0b10000010>; |
| 36 | class DPAU_H_QBR_MM_ENC : POOL32A_AC2R_FMT<"dpau.h.qbr", 0b11000010>; |
| 37 | class DPAX_W_PH_MMR2_ENC : POOL32A_AC2R_FMT<"dpax.w.ph", 0b01000010>; |
| Zlatko Buljan | d0a7d6e | 2015-10-19 06:34:44 +0000 | [diff] [blame] | 38 | class ABSQ_S_PH_MM_ENC : POOL32A_2R_FMT<"absq_s.ph", 0b0001000100>; |
| 39 | class ABSQ_S_W_MM_ENC : POOL32A_2R_FMT<"absq_s.w", 0b0010000100>; |
| 40 | class ABSQ_S_QB_MMR2_ENC : POOL32A_2R_FMT<"absq_s.qb", 0b0000000100>; |
| 41 | class INSV_MM_ENC : POOL32A_2R_FMT<"insv", 0b0100000100>; |
| 42 | class MADD_DSP_MM_ENC : POOL32A_2RAC_FMT<"madd", 0b00101010>; |
| 43 | class MADDU_DSP_MM_ENC : POOL32A_2RAC_FMT<"maddu", 0b01101010>; |
| 44 | class MSUB_DSP_MM_ENC : POOL32A_2RAC_FMT<"msub", 0b10101010>; |
| 45 | class MSUBU_DSP_MM_ENC : POOL32A_2RAC_FMT<"msubu", 0b11101010>; |
| 46 | class MULT_DSP_MM_ENC : POOL32A_2RAC_FMT<"mult", 0b00110010>; |
| 47 | class MULTU_DSP_MM_ENC : POOL32A_2RAC_FMT<"multu", 0b01110010>; |
| Zoran Jovanovic | 2e386d3 | 2015-10-12 16:07:25 +0000 | [diff] [blame] | 48 | |
| 49 | // Instruction defs. |
| Zlatko Buljan | d0a7d6e | 2015-10-19 06:34:44 +0000 | [diff] [blame] | 50 | class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode, |
| 51 | InstrItinClass itin, RegisterOperand ROD, |
| 52 | RegisterOperand ROS = ROD> { |
| 53 | dag OutOperandList = (outs ROD:$rt); |
| 54 | dag InOperandList = (ins ROS:$rs); |
| 55 | string AsmString = !strconcat(opstr, "\t$rt, $rs"); |
| 56 | list<dag> Pattern = [(set ROD:$rt, (OpNode ROS:$rs))]; |
| 57 | InstrItinClass Itinerary = itin; |
| 58 | } |
| 59 | class ABSQ_S_PH_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< |
| 60 | "absq_s.ph", int_mips_absq_s_ph, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>; |
| 61 | class ABSQ_S_W_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< |
| 62 | "absq_s.w", int_mips_absq_s_w, NoItinerary, GPR32Opnd>, Defs<[DSPOutFlag20]>; |
| 63 | class ABSQ_S_QB_MMR2_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< |
| 64 | "absq_s.qb", int_mips_absq_s_qb, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>; |
| 65 | |
| Zlatko Buljan | 54b1eb4 | 2015-10-15 08:59:45 +0000 | [diff] [blame] | 66 | // microMIPS DSP Rev 1 |
| Zlatko Buljan | 5292083 | 2015-10-19 07:16:26 +0000 | [diff] [blame^] | 67 | def ADDQ_PH_MM : DspMMRel, ADDQ_PH_MM_ENC, ADDQ_PH_DESC; |
| 68 | def ADDQ_S_PH_MM : DspMMRel, ADDQ_S_PH_MM_ENC, ADDQ_S_PH_DESC; |
| 69 | def ADDQ_S_W_MM : DspMMRel, ADDQ_S_W_MM_ENC, ADDQ_S_W_DESC; |
| Zlatko Buljan | 54b1eb4 | 2015-10-15 08:59:45 +0000 | [diff] [blame] | 70 | def ADDU_QB_MM : DspMMRel, ADDU_QB_MM_ENC, ADDU_QB_DESC; |
| Zlatko Buljan | 5292083 | 2015-10-19 07:16:26 +0000 | [diff] [blame^] | 71 | def ADDU_S_QB_MM : DspMMRel, ADDU_S_QB_MM_ENC, ADDU_S_QB_DESC; |
| 72 | def ADDSC_MM : DspMMRel, ADDSC_MM_ENC, ADDSC_DESC; |
| 73 | def ADDWC_MM : DspMMRel, ADDWC_MM_ENC, ADDWC_DESC; |
| Zlatko Buljan | 54b1eb4 | 2015-10-15 08:59:45 +0000 | [diff] [blame] | 74 | def DPAQ_S_W_PH_MM : DspMMRel, DPAQ_S_W_PH_MM_ENC, DPAQ_S_W_PH_DESC; |
| 75 | def DPAQ_SA_L_W_MM : DspMMRel, DPAQ_SA_L_W_MM_ENC, DPAQ_SA_L_W_DESC; |
| 76 | def DPAU_H_QBL_MM : DspMMRel, DPAU_H_QBL_MM_ENC, DPAU_H_QBL_DESC; |
| 77 | def DPAU_H_QBR_MM : DspMMRel, DPAU_H_QBR_MM_ENC, DPAU_H_QBR_DESC; |
| Zlatko Buljan | d0a7d6e | 2015-10-19 06:34:44 +0000 | [diff] [blame] | 78 | def ABSQ_S_PH_MM : DspMMRel, ABSQ_S_PH_MM_ENC, ABSQ_S_PH_MM_DESC; |
| 79 | def ABSQ_S_W_MM : DspMMRel, ABSQ_S_W_MM_ENC, ABSQ_S_W_MM_DESC; |
| 80 | def INSV_MM : DspMMRel, INSV_MM_ENC, INSV_DESC; |
| 81 | def MADD_DSP_MM : DspMMRel, MADD_DSP_MM_ENC, MADD_DSP_DESC; |
| 82 | def MADDU_DSP_MM : DspMMRel, MADDU_DSP_MM_ENC, MADDU_DSP_DESC; |
| 83 | def MSUB_DSP_MM : DspMMRel, MSUB_DSP_MM_ENC, MSUB_DSP_DESC; |
| 84 | def MSUBU_DSP_MM : DspMMRel, MSUBU_DSP_MM_ENC, MSUBU_DSP_DESC; |
| 85 | def MULT_DSP_MM : DspMMRel, MULT_DSP_MM_ENC, MULT_DSP_DESC; |
| 86 | def MULTU_DSP_MM : DspMMRel, MULTU_DSP_MM_ENC, MULTU_DSP_DESC; |
| 87 | // microMIPS DSP Rev 2 |
| 88 | def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC, |
| 89 | ISA_DSPR2; |
| Zlatko Buljan | 5292083 | 2015-10-19 07:16:26 +0000 | [diff] [blame^] | 90 | def ADDQH_PH_MMR2 : DspMMRel, ADDQH_PH_MMR2_ENC, ADDQH_PH_DESC, ISA_DSPR2; |
| 91 | def ADDQH_R_PH_MMR2 : DspMMRel, ADDQH_R_PH_MMR2_ENC, ADDQH_R_PH_DESC, ISA_DSPR2; |
| 92 | def ADDQH_W_MMR2 : DspMMRel, ADDQH_W_MMR2_ENC, ADDQH_W_DESC, ISA_DSPR2; |
| 93 | def ADDQH_R_W_MMR2 : DspMMRel, ADDQH_R_W_MMR2_ENC, ADDQH_R_W_DESC, ISA_DSPR2; |
| 94 | def ADDU_PH_MMR2 : DspMMRel, ADDU_PH_MMR2_ENC, ADDU_PH_DESC, ISA_DSPR2; |
| 95 | def ADDU_S_PH_MMR2 : DspMMRel, ADDU_S_PH_MMR2_ENC, ADDU_S_PH_DESC, ISA_DSPR2; |
| 96 | def ADDUH_QB_MMR2 : DspMMRel, ADDUH_QB_MMR2_ENC, ADDUH_QB_DESC, ISA_DSPR2; |
| 97 | def ADDUH_R_QB_MMR2 : DspMMRel, ADDUH_R_QB_MMR2_ENC, ADDUH_R_QB_DESC, ISA_DSPR2; |
| 98 | def DPA_W_PH_MMR2 : DspMMRel, DPA_W_PH_MMR2_ENC, DPA_W_PH_DESC, ISA_DSPR2; |
| 99 | def DPAQX_S_W_PH_MMR2 : DspMMRel, DPAQX_S_W_PH_MMR2_ENC, DPAQX_S_W_PH_DESC, |
| 100 | ISA_DSPR2; |
| 101 | def DPAQX_SA_W_PH_MMR2 : DspMMRel, DPAQX_SA_W_PH_MMR2_ENC, DPAQX_SA_W_PH_DESC, |
| 102 | ISA_DSPR2; |
| 103 | def DPAX_W_PH_MMR2 : DspMMRel, DPAX_W_PH_MMR2_ENC, DPAX_W_PH_DESC, ISA_DSPR2; |