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gerrit-public.fairphone.software / toolchain / llvm-project / 59136ffab1b0b051d2b56a90b8fb86d5721ed0b5 / . / llvm / test / CodeGen / RISCV / addc-adde-sube-subc.ll
blob: fd22e310f10ad87d04439ed4f286ed3efdc52df5 [file] [log] [blame]
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN: | FileCheck -check-prefix=RV32I %s
4
5; Ensure that the ISDOpcodes ADDC, ADDE, SUBC, SUBE are handled correctly
6
7define i64 @addc_adde(i64 %a, i64 %b) {
8; RV32I-LABEL: addc_adde:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9; RV32I: # %bb.0:
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]10; RV32I-NEXT: addi sp, sp, -16
11; RV32I-NEXT: sw ra, 12(sp)
12; RV32I-NEXT: sw s0, 8(sp)
13; RV32I-NEXT: addi s0, sp, 16
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]14; RV32I-NEXT: add a1, a1, a3
15; RV32I-NEXT: add a2, a0, a2
16; RV32I-NEXT: sltu a0, a2, a0
17; RV32I-NEXT: add a1, a1, a0
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]18; RV32I-NEXT: mv a0, a2
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]19; RV32I-NEXT: lw s0, 8(sp)
20; RV32I-NEXT: lw ra, 12(sp)
21; RV32I-NEXT: addi sp, sp, 16
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]22; RV32I-NEXT: ret
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]23 %1 = add i64 %a, %b
24 ret i64 %1
25}
26
27define i64 @subc_sube(i64 %a, i64 %b) {
28; RV32I-LABEL: subc_sube:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]29; RV32I: # %bb.0:
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]30; RV32I-NEXT: addi sp, sp, -16
31; RV32I-NEXT: sw ra, 12(sp)
32; RV32I-NEXT: sw s0, 8(sp)
33; RV32I-NEXT: addi s0, sp, 16
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]34; RV32I-NEXT: sub a1, a1, a3
35; RV32I-NEXT: sltu a3, a0, a2
36; RV32I-NEXT: sub a1, a1, a3
37; RV32I-NEXT: sub a0, a0, a2
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]38; RV32I-NEXT: lw s0, 8(sp)
39; RV32I-NEXT: lw ra, 12(sp)
40; RV32I-NEXT: addi sp, sp, 16
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]41; RV32I-NEXT: ret
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]42 %1 = sub i64 %a, %b
43 ret i64 %1
44}