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gerrit-public.fairphone.software / toolchain / llvm-project / 59136ffab1b0b051d2b56a90b8fb86d5721ed0b5 / . / llvm / test / CodeGen / RISCV / imm.ll
blob: 6741c3cb04a5c9638df3be9fb0c852855f1cc11f [file] [log] [blame]
Alex Bradbury0f0e1b52017-11-08 12:02:22 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN: | FileCheck %s -check-prefix=RV32I
4
5; Materializing constants
6
7define i32 @zero() nounwind {
8; RV32I-LABEL: zero:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]9; RV32I: # %bb.0:
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]10; RV32I-NEXT: addi sp, sp, -16
11; RV32I-NEXT: sw ra, 12(sp)
12; RV32I-NEXT: sw s0, 8(sp)
13; RV32I-NEXT: addi s0, sp, 16
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]14; RV32I-NEXT: mv a0, zero
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]15; RV32I-NEXT: lw s0, 8(sp)
16; RV32I-NEXT: lw ra, 12(sp)
17; RV32I-NEXT: addi sp, sp, 16
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]18; RV32I-NEXT: ret
Alex Bradbury0f0e1b52017-11-08 12:02:22 +0000[diff] [blame]19 ret i32 0
20}
21
22define i32 @pos_small() nounwind {
23; RV32I-LABEL: pos_small:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]24; RV32I: # %bb.0:
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]25; RV32I-NEXT: addi sp, sp, -16
26; RV32I-NEXT: sw ra, 12(sp)
27; RV32I-NEXT: sw s0, 8(sp)
28; RV32I-NEXT: addi s0, sp, 16
Alex Bradbury0f0e1b52017-11-08 12:02:22 +0000[diff] [blame]29; RV32I-NEXT: addi a0, zero, 2047
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]30; RV32I-NEXT: lw s0, 8(sp)
31; RV32I-NEXT: lw ra, 12(sp)
32; RV32I-NEXT: addi sp, sp, 16
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]33; RV32I-NEXT: ret
Alex Bradbury0f0e1b52017-11-08 12:02:22 +0000[diff] [blame]34 ret i32 2047
35}
36
37define i32 @neg_small() nounwind {
38; RV32I-LABEL: neg_small:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]39; RV32I: # %bb.0:
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]40; RV32I-NEXT: addi sp, sp, -16
41; RV32I-NEXT: sw ra, 12(sp)
42; RV32I-NEXT: sw s0, 8(sp)
43; RV32I-NEXT: addi s0, sp, 16
Alex Bradbury0f0e1b52017-11-08 12:02:22 +0000[diff] [blame]44; RV32I-NEXT: addi a0, zero, -2048
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]45; RV32I-NEXT: lw s0, 8(sp)
46; RV32I-NEXT: lw ra, 12(sp)
47; RV32I-NEXT: addi sp, sp, 16
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]48; RV32I-NEXT: ret
Alex Bradbury0f0e1b52017-11-08 12:02:22 +0000[diff] [blame]49 ret i32 -2048
50}
51
52define i32 @pos_i32() nounwind {
53; RV32I-LABEL: pos_i32:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]54; RV32I: # %bb.0:
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]55; RV32I-NEXT: addi sp, sp, -16
56; RV32I-NEXT: sw ra, 12(sp)
57; RV32I-NEXT: sw s0, 8(sp)
58; RV32I-NEXT: addi s0, sp, 16
Alex Bradbury0f0e1b52017-11-08 12:02:22 +0000[diff] [blame]59; RV32I-NEXT: lui a0, 423811
60; RV32I-NEXT: addi a0, a0, -1297
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]61; RV32I-NEXT: lw s0, 8(sp)
62; RV32I-NEXT: lw ra, 12(sp)
63; RV32I-NEXT: addi sp, sp, 16
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]64; RV32I-NEXT: ret
Alex Bradbury0f0e1b52017-11-08 12:02:22 +0000[diff] [blame]65 ret i32 1735928559
66}
67
68define i32 @neg_i32() nounwind {
69; RV32I-LABEL: neg_i32:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]70; RV32I: # %bb.0:
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]71; RV32I-NEXT: addi sp, sp, -16
72; RV32I-NEXT: sw ra, 12(sp)
73; RV32I-NEXT: sw s0, 8(sp)
74; RV32I-NEXT: addi s0, sp, 16
Alex Bradbury0f0e1b52017-11-08 12:02:22 +0000[diff] [blame]75; RV32I-NEXT: lui a0, 912092
76; RV32I-NEXT: addi a0, a0, -273
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]77; RV32I-NEXT: lw s0, 8(sp)
78; RV32I-NEXT: lw ra, 12(sp)
79; RV32I-NEXT: addi sp, sp, 16
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]80; RV32I-NEXT: ret
Alex Bradbury0f0e1b52017-11-08 12:02:22 +0000[diff] [blame]81 ret i32 -559038737
82}