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gerrit-public.fairphone.software / toolchain / llvm-project / 59136ffab1b0b051d2b56a90b8fb86d5721ed0b5 / . / llvm / test / CodeGen / RISCV / indirectbr.ll
blob: 47ce5c18c32d2a1f5012636928b03006ae66c047 [file] [log] [blame]
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN: | FileCheck %s -check-prefix=RV32I
4
5define i32 @indirectbr(i8* %target) nounwind {
6; RV32I-LABEL: indirectbr:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7; RV32I: # %bb.0:
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]8; RV32I-NEXT: addi sp, sp, -16
9; RV32I-NEXT: sw ra, 12(sp)
10; RV32I-NEXT: sw s0, 8(sp)
11; RV32I-NEXT: addi s0, sp, 16
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]12; RV32I-NEXT: jr a0
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]13; RV32I-NEXT: .LBB0_1: # %ret
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]14; RV32I-NEXT: mv a0, zero
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]15; RV32I-NEXT: lw s0, 8(sp)
16; RV32I-NEXT: lw ra, 12(sp)
17; RV32I-NEXT: addi sp, sp, 16
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]18; RV32I-NEXT: ret
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]19 indirectbr i8* %target, [label %test_label]
20test_label:
21 br label %ret
22ret:
23 ret i32 0
24}
25
26define i32 @indirectbr_with_offset(i8* %a) nounwind {
27; RV32I-LABEL: indirectbr_with_offset:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]28; RV32I: # %bb.0:
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]29; RV32I-NEXT: addi sp, sp, -16
30; RV32I-NEXT: sw ra, 12(sp)
31; RV32I-NEXT: sw s0, 8(sp)
32; RV32I-NEXT: addi s0, sp, 16
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]33; RV32I-NEXT: jalr zero, a0, 1380
34; RV32I-NEXT: .LBB1_1: # %ret
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]35; RV32I-NEXT: mv a0, zero
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]36; RV32I-NEXT: lw s0, 8(sp)
37; RV32I-NEXT: lw ra, 12(sp)
38; RV32I-NEXT: addi sp, sp, 16
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]39; RV32I-NEXT: ret
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]40 %target = getelementptr inbounds i8, i8* %a, i32 1380
41 indirectbr i8* %target, [label %test_label]
42test_label:
43 br label %ret
44ret:
45 ret i32 0
46}