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gerrit-public.fairphone.software / toolchain / llvm-project / 59136ffab1b0b051d2b56a90b8fb86d5721ed0b5 / . / llvm / test / CodeGen / RISCV / jumptable.ll
blob: 8240f43805cbdeea3aa46c407ec8472eb58d75c3 [file] [log] [blame]
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN: | FileCheck %s -check-prefix=RV32I
4
5define void @jt(i32 %in, i32* %out) {
6; RV32I-LABEL: jt:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7; RV32I: # %bb.0: # %entry
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]8; RV32I-NEXT: addi sp, sp, -16
9; RV32I-NEXT: sw ra, 12(sp)
10; RV32I-NEXT: sw s0, 8(sp)
11; RV32I-NEXT: addi s0, sp, 16
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]12; RV32I-NEXT: addi a2, zero, 2
13; RV32I-NEXT: blt a2, a0, .LBB0_3
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]14; RV32I-NEXT: j .LBB0_1
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]15; RV32I-NEXT: .LBB0_1: # %entry
16; RV32I-NEXT: addi a3, zero, 1
17; RV32I-NEXT: beq a0, a3, .LBB0_5
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]18; RV32I-NEXT: j .LBB0_2
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]19; RV32I-NEXT: .LBB0_2: # %entry
20; RV32I-NEXT: beq a0, a2, .LBB0_6
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]21; RV32I-NEXT: j .LBB0_9
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]22; RV32I-NEXT: .LBB0_6: # %bb2
23; RV32I-NEXT: addi a0, zero, 3
24; RV32I-NEXT: sw a0, 0(a1)
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]25; RV32I-NEXT: j .LBB0_9
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]26; RV32I-NEXT: .LBB0_3: # %entry
27; RV32I-NEXT: addi a3, zero, 3
28; RV32I-NEXT: beq a0, a3, .LBB0_7
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]29; RV32I-NEXT: j .LBB0_4
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]30; RV32I-NEXT: .LBB0_4: # %entry
31; RV32I-NEXT: addi a2, zero, 4
32; RV32I-NEXT: beq a0, a2, .LBB0_8
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]33; RV32I-NEXT: j .LBB0_9
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]34; RV32I-NEXT: .LBB0_8: # %bb4
35; RV32I-NEXT: addi a0, zero, 1
36; RV32I-NEXT: sw a0, 0(a1)
37; RV32I-NEXT: .LBB0_9: # %exit
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]38; RV32I-NEXT: lw s0, 8(sp)
39; RV32I-NEXT: lw ra, 12(sp)
40; RV32I-NEXT: addi sp, sp, 16
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]41; RV32I-NEXT: ret
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]42; RV32I-NEXT: .LBB0_5: # %bb1
43; RV32I-NEXT: addi a0, zero, 4
44; RV32I-NEXT: sw a0, 0(a1)
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]45; RV32I-NEXT: j .LBB0_9
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]46; RV32I-NEXT: .LBB0_7: # %bb3
47; RV32I-NEXT: sw a2, 0(a1)
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]48; RV32I-NEXT: j .LBB0_9
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]49entry:
50 switch i32 %in, label %exit [
51 i32 1, label %bb1
52 i32 2, label %bb2
53 i32 3, label %bb3
54 i32 4, label %bb4
55 ]
56bb1:
57 store i32 4, i32* %out
58 br label %exit
59bb2:
60 store i32 3, i32* %out
61 br label %exit
62bb3:
63 store i32 2, i32* %out
64 br label %exit
65bb4:
66 store i32 1, i32* %out
67 br label %exit
68exit:
69 ret void
70}