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gerrit-public.fairphone.software / toolchain / llvm-project / 59136ffab1b0b051d2b56a90b8fb86d5721ed0b5 / . / llvm / test / CodeGen / RISCV / select-cc.ll
blob: 1bdc8cba18721984db1abdcfca69ca5e54d0c064 [file] [log] [blame]
Alex Bradbury65385162017-11-21 07:51:32 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN: | FileCheck -check-prefix=RV32I %s
4
5define i32 @foo(i32 %a, i32 *%b) {
6; RV32I-LABEL: foo:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7; RV32I: # %bb.0:
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]8; RV32I-NEXT: addi sp, sp, -16
9; RV32I-NEXT: sw ra, 12(sp)
10; RV32I-NEXT: sw s0, 8(sp)
11; RV32I-NEXT: addi s0, sp, 16
Alex Bradbury65385162017-11-21 07:51:32 +0000[diff] [blame]12; RV32I-NEXT: lw a2, 0(a1)
13; RV32I-NEXT: beq a0, a2, .LBB0_2
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]14; RV32I-NEXT: # %bb.1:
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]15; RV32I-NEXT: mv a0, a2
Alex Bradbury65385162017-11-21 07:51:32 +0000[diff] [blame]16; RV32I-NEXT: .LBB0_2:
17; RV32I-NEXT: lw a2, 0(a1)
18; RV32I-NEXT: bne a0, a2, .LBB0_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]19; RV32I-NEXT: # %bb.3:
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]20; RV32I-NEXT: mv a0, a2
Alex Bradbury65385162017-11-21 07:51:32 +0000[diff] [blame]21; RV32I-NEXT: .LBB0_4:
22; RV32I-NEXT: lw a2, 0(a1)
23; RV32I-NEXT: bltu a2, a0, .LBB0_6
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]24; RV32I-NEXT: # %bb.5:
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]25; RV32I-NEXT: mv a0, a2
Alex Bradbury65385162017-11-21 07:51:32 +0000[diff] [blame]26; RV32I-NEXT: .LBB0_6:
27; RV32I-NEXT: lw a2, 0(a1)
28; RV32I-NEXT: bgeu a0, a2, .LBB0_8
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]29; RV32I-NEXT: # %bb.7:
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]30; RV32I-NEXT: mv a0, a2
Alex Bradbury65385162017-11-21 07:51:32 +0000[diff] [blame]31; RV32I-NEXT: .LBB0_8:
32; RV32I-NEXT: lw a2, 0(a1)
33; RV32I-NEXT: bltu a0, a2, .LBB0_10
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]34; RV32I-NEXT: # %bb.9:
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]35; RV32I-NEXT: mv a0, a2
Alex Bradbury65385162017-11-21 07:51:32 +0000[diff] [blame]36; RV32I-NEXT: .LBB0_10:
37; RV32I-NEXT: lw a2, 0(a1)
38; RV32I-NEXT: bgeu a2, a0, .LBB0_12
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]39; RV32I-NEXT: # %bb.11:
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]40; RV32I-NEXT: mv a0, a2
Alex Bradbury65385162017-11-21 07:51:32 +0000[diff] [blame]41; RV32I-NEXT: .LBB0_12:
42; RV32I-NEXT: lw a2, 0(a1)
43; RV32I-NEXT: blt a2, a0, .LBB0_14
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]44; RV32I-NEXT: # %bb.13:
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]45; RV32I-NEXT: mv a0, a2
Alex Bradbury65385162017-11-21 07:51:32 +0000[diff] [blame]46; RV32I-NEXT: .LBB0_14:
47; RV32I-NEXT: lw a2, 0(a1)
48; RV32I-NEXT: bge a0, a2, .LBB0_16
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]49; RV32I-NEXT: # %bb.15:
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]50; RV32I-NEXT: mv a0, a2
Alex Bradbury65385162017-11-21 07:51:32 +0000[diff] [blame]51; RV32I-NEXT: .LBB0_16:
52; RV32I-NEXT: lw a2, 0(a1)
53; RV32I-NEXT: blt a0, a2, .LBB0_18
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]54; RV32I-NEXT: # %bb.17:
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]55; RV32I-NEXT: mv a0, a2
Alex Bradbury65385162017-11-21 07:51:32 +0000[diff] [blame]56; RV32I-NEXT: .LBB0_18:
57; RV32I-NEXT: lw a1, 0(a1)
58; RV32I-NEXT: bge a1, a0, .LBB0_20
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]59; RV32I-NEXT: # %bb.19:
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]60; RV32I-NEXT: mv a0, a1
Alex Bradbury65385162017-11-21 07:51:32 +0000[diff] [blame]61; RV32I-NEXT: .LBB0_20:
Alex Bradburyb014e3d2017-12-11 12:34:11 +0000[diff] [blame]62; RV32I-NEXT: lw s0, 8(sp)
63; RV32I-NEXT: lw ra, 12(sp)
64; RV32I-NEXT: addi sp, sp, 16
Alex Bradbury59136ff2017-12-15 09:47:01 +0000[diff] [blame^]65; RV32I-NEXT: ret
Alex Bradbury65385162017-11-21 07:51:32 +0000[diff] [blame]66 %val1 = load volatile i32, i32* %b
67 %tst1 = icmp eq i32 %a, %val1
68 %val2 = select i1 %tst1, i32 %a, i32 %val1
69
70 %val3 = load volatile i32, i32* %b
71 %tst2 = icmp ne i32 %val2, %val3
72 %val4 = select i1 %tst2, i32 %val2, i32 %val3
73
74 %val5 = load volatile i32, i32* %b
75 %tst3 = icmp ugt i32 %val4, %val5
76 %val6 = select i1 %tst3, i32 %val4, i32 %val5
77
78 %val7 = load volatile i32, i32* %b
79 %tst4 = icmp uge i32 %val6, %val7
80 %val8 = select i1 %tst4, i32 %val6, i32 %val7
81
82 %val9 = load volatile i32, i32* %b
83 %tst5 = icmp ult i32 %val8, %val9
84 %val10 = select i1 %tst5, i32 %val8, i32 %val9
85
86 %val11 = load volatile i32, i32* %b
87 %tst6 = icmp ule i32 %val10, %val11
88 %val12 = select i1 %tst6, i32 %val10, i32 %val11
89
90 %val13 = load volatile i32, i32* %b
91 %tst7 = icmp sgt i32 %val12, %val13
92 %val14 = select i1 %tst7, i32 %val12, i32 %val13
93
94 %val15 = load volatile i32, i32* %b
95 %tst8 = icmp sge i32 %val14, %val15
96 %val16 = select i1 %tst8, i32 %val14, i32 %val15
97
98 %val17 = load volatile i32, i32* %b
99 %tst9 = icmp slt i32 %val16, %val17
100 %val18 = select i1 %tst9, i32 %val16, i32 %val17
101
102 %val19 = load volatile i32, i32* %b
103 %tst10 = icmp sle i32 %val18, %val19
104 %val20 = select i1 %tst10, i32 %val18, i32 %val19
105
106 ret i32 %val20
107}