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Matt Arsenault0c90e952015-11-06 18:17:45 +00001//===--------------------- SIFrameLowering.h --------------------*- C++ -*-===//
2//
Chandler Carruth2946cd72019-01-19 08:50:56 +00003// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Matt Arsenault0c90e952015-11-06 18:17:45 +00006//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H
10#define LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H
11
12#include "AMDGPUFrameLowering.h"
13
14namespace llvm {
Eugene Zelenko2bc2f332016-12-09 22:06:55 +000015
Matt Arsenault57bc4322016-08-31 21:52:21 +000016class SIInstrInfo;
17class SIMachineFunctionInfo;
18class SIRegisterInfo;
Tom Stellard5bfbae52018-07-11 20:59:01 +000019class GCNSubtarget;
Matt Arsenault0c90e952015-11-06 18:17:45 +000020
21class SIFrameLowering final : public AMDGPUFrameLowering {
22public:
23 SIFrameLowering(StackDirection D, unsigned StackAl, int LAO,
24 unsigned TransAl = 1) :
25 AMDGPUFrameLowering(D, StackAl, LAO, TransAl) {}
Eugene Zelenko2bc2f332016-12-09 22:06:55 +000026 ~SIFrameLowering() override = default;
Matt Arsenault0c90e952015-11-06 18:17:45 +000027
Matt Arsenault2b1f9aa2017-05-17 21:56:25 +000028 void emitEntryFunctionPrologue(MachineFunction &MF,
29 MachineBasicBlock &MBB) const;
Matt Arsenault0e3d3892015-11-30 21:15:53 +000030 void emitPrologue(MachineFunction &MF,
31 MachineBasicBlock &MBB) const override;
Matt Arsenault43e92fe2016-06-24 06:30:11 +000032 void emitEpilogue(MachineFunction &MF,
33 MachineBasicBlock &MBB) const override;
Konstantin Zhuravlyovffdb00e2017-03-10 19:39:07 +000034 int getFrameIndexReference(const MachineFunction &MF, int FI,
35 unsigned &FrameReg) const override;
Matt Arsenault0e3d3892015-11-30 21:15:53 +000036
Matt Arsenaultecb43ef2017-09-13 23:47:01 +000037 void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
38 RegScavenger *RS = nullptr) const override;
Matt Arsenault5b0922f2019-07-03 23:32:29 +000039 void determineCalleeSavesSGPR(MachineFunction &MF, BitVector &SavedRegs,
40 RegScavenger *RS = nullptr) const;
Matt Arsenaultecb43ef2017-09-13 23:47:01 +000041
Sander de Smalen5d6ee762019-06-17 09:13:29 +000042 bool isSupportedStackID(TargetStackID::Value ID) const override;
43
Matt Arsenault0c90e952015-11-06 18:17:45 +000044 void processFunctionBeforeFrameFinalized(
45 MachineFunction &MF,
46 RegScavenger *RS = nullptr) const override;
Konstantin Zhuravlyovf2f3d142016-06-25 03:11:28 +000047
Matt Arsenaultb62a4eb2017-08-01 19:54:18 +000048 MachineBasicBlock::iterator
49 eliminateCallFramePseudoInstr(MachineFunction &MF,
50 MachineBasicBlock &MBB,
51 MachineBasicBlock::iterator MI) const override;
52
Konstantin Zhuravlyovf2f3d142016-06-25 03:11:28 +000053private:
Tom Stellard5bfbae52018-07-11 20:59:01 +000054 void emitFlatScratchInit(const GCNSubtarget &ST,
Matt Arsenault57bc4322016-08-31 21:52:21 +000055 MachineFunction &MF,
56 MachineBasicBlock &MBB) const;
57
58 unsigned getReservedPrivateSegmentBufferReg(
Tom Stellard5bfbae52018-07-11 20:59:01 +000059 const GCNSubtarget &ST,
Matt Arsenault57bc4322016-08-31 21:52:21 +000060 const SIInstrInfo *TII,
61 const SIRegisterInfo *TRI,
62 SIMachineFunctionInfo *MFI,
63 MachineFunction &MF) const;
64
Matt Arsenaultb812b7a2019-06-05 22:20:47 +000065 unsigned getReservedPrivateSegmentWaveByteOffsetReg(
66 const GCNSubtarget &ST, const SIInstrInfo *TII, const SIRegisterInfo *TRI,
67 SIMachineFunctionInfo *MFI, MachineFunction &MF) const;
Matt Arsenault57bc4322016-08-31 21:52:21 +000068
Tim Renouf13229152017-09-29 09:49:35 +000069 // Emit scratch setup code for AMDPAL or Mesa, assuming ResourceRegUsed is set.
Tom Stellard5bfbae52018-07-11 20:59:01 +000070 void emitEntryFunctionScratchSetup(const GCNSubtarget &ST, MachineFunction &MF,
Tim Renouf13229152017-09-29 09:49:35 +000071 MachineBasicBlock &MBB, SIMachineFunctionInfo *MFI,
72 MachineBasicBlock::iterator I, unsigned PreloadedPrivateBufferReg,
73 unsigned ScratchRsrcReg) const;
74
Matt Arsenaultf28683c2017-06-26 17:53:59 +000075public:
76 bool hasFP(const MachineFunction &MF) const override;
Matt Arsenault0c90e952015-11-06 18:17:45 +000077};
78
Eugene Zelenko2bc2f332016-12-09 22:06:55 +000079} // end namespace llvm
Matt Arsenault0c90e952015-11-06 18:17:45 +000080
Eugene Zelenko2bc2f332016-12-09 22:06:55 +000081#endif // LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H