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Rafael Espindolaffdc24b2006-05-14 22:18:28 +00001//===- ARMInstrInfo.td - Target Description for ARM Target ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the "Instituto Nokia de Tecnologia" and
6// is distributed under the University of Illinois Open Source
7// License. See LICENSE.TXT for details.
8//
9//===----------------------------------------------------------------------===//
10//
11// This file describes the ARM instructions in TableGen format.
12//
13//===----------------------------------------------------------------------===//
14
15
16
17//===----------------------------------------------------------------------===//
18// Instructions
19//===----------------------------------------------------------------------===//
20
21class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction {
22 let Namespace = "ARM";
23
24 dag OperandList = ops;
25 let AsmString = asmstr;
26 let Pattern = pattern;
27}
28
29def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
30def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq, [SDNPHasChain]>;
31def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq, [SDNPHasChain]>;
32
Rafael Espindolaffdc24b2006-05-14 22:18:28 +000033def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
34 "!ADJCALLSTACKUP $amt",
35 [(callseq_end imm:$amt)]>;
36
37def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
38 "!ADJCALLSTACKDOWN $amt",
39 [(callseq_start imm:$amt)]>;
40
Rafael Espindola5bc60da2006-05-30 17:33:19 +000041def bxr: InstARM<(ops IntRegs:$dst), "bx $dst", [(brind IntRegs:$dst)]>;
Rafael Espindolab15597b2006-05-18 21:45:49 +000042
Rafael Espindolaffdc24b2006-05-14 22:18:28 +000043def ldr : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
44 "ldr $dst, [$addr]",
45 [(set IntRegs:$dst, (load IntRegs:$addr))]>;
46
47def str : InstARM<(ops IntRegs:$src, IntRegs:$addr),
48 "str $src, [$addr]",
49 [(store IntRegs:$src, IntRegs:$addr)]>;
50
Rafael Espindolab15597b2006-05-18 21:45:49 +000051def movrr : InstARM<(ops IntRegs:$dst, IntRegs:$src),
52 "mov $dst, $src", []>;
53
54def movri : InstARM<(ops IntRegs:$dst, i32imm:$src),
55 "mov $dst, $src", [(set IntRegs:$dst, imm:$src)]>;