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Tom Stellard75aadc22012-12-11 21:25:42 +00001//===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
Adrian Prantl5f8f34e42018-05-01 15:54:18 +000011/// Contains the definition of a TargetInstrInfo class that is common
Tom Stellard75aadc22012-12-11 21:25:42 +000012/// to all AMD GPUs.
13//
14//===----------------------------------------------------------------------===//
15
Matt Arsenault6b6a2c32016-03-11 08:00:27 +000016#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
17#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
Tom Stellard75aadc22012-12-11 21:25:42 +000018
Yaxun Liu1a14bfa2017-03-27 14:04:01 +000019#include "AMDGPU.h"
Sam Koltona3ec5c12016-10-07 14:46:06 +000020#include "Utils/AMDGPUBaseInfo.h"
David Blaikie3f833ed2017-11-08 01:01:31 +000021#include "llvm/CodeGen/TargetInstrInfo.h"
Tom Stellard75aadc22012-12-11 21:25:42 +000022
Tom Stellard75aadc22012-12-11 21:25:42 +000023namespace llvm {
24
Tom Stellard5bfbae52018-07-11 20:59:01 +000025class GCNSubtarget;
Tom Stellard75aadc22012-12-11 21:25:42 +000026class MachineFunction;
27class MachineInstr;
28class MachineInstrBuilder;
29
Tom Stellardc5a154d2018-06-28 23:47:12 +000030class AMDGPUInstrInfo {
Tom Stellard75aadc22012-12-11 21:25:42 +000031public:
Tom Stellard5bfbae52018-07-11 20:59:01 +000032 explicit AMDGPUInstrInfo(const GCNSubtarget &st);
Tom Stellard75aadc22012-12-11 21:25:42 +000033
Matt Arsenaultbcf7bec2018-02-09 16:57:48 +000034 static bool isUniformMMO(const MachineMemOperand *MMO);
Tom Stellard75aadc22012-12-11 21:25:42 +000035};
Nicolai Haehnle5d0d3032018-04-01 17:09:07 +000036
37namespace AMDGPU {
38
39struct RsrcIntrinsic {
40 unsigned Intr;
41 uint8_t RsrcArg;
42 bool IsImage;
43};
Nicolai Haehnlee741d7e2018-06-21 13:36:33 +000044const RsrcIntrinsic *lookupRsrcIntrinsic(unsigned Intr);
Nicolai Haehnle5d0d3032018-04-01 17:09:07 +000045
Nicolai Haehnle2f5a7382018-04-04 10:58:54 +000046struct D16ImageDimIntrinsic {
47 unsigned Intr;
48 unsigned D16HelperIntr;
49};
Nicolai Haehnlee741d7e2018-06-21 13:36:33 +000050const D16ImageDimIntrinsic *lookupD16ImageDimIntrinsic(unsigned Intr);
Nicolai Haehnle2f5a7382018-04-04 10:58:54 +000051
Nicolai Haehnle7a9c03f2018-06-21 13:36:57 +000052struct ImageDimIntrinsicInfo {
53 unsigned Intr;
54 unsigned BaseOpcode;
55 MIMGDim Dim;
56};
57const ImageDimIntrinsicInfo *getImageDimIntrinsicInfo(unsigned Intr);
58
Nicolai Haehnle5d0d3032018-04-01 17:09:07 +000059} // end AMDGPU namespace
Alexander Kornienkof00654e2015-06-23 09:49:53 +000060} // End llvm namespace
Tom Stellard75aadc22012-12-11 21:25:42 +000061
Benjamin Kramera7c40ef2014-08-13 16:26:38 +000062#endif