| Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 1 | //===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | /// \file |
| Adrian Prantl | 5f8f34e4 | 2018-05-01 15:54:18 +0000 | [diff] [blame] | 11 | /// Contains the definition of a TargetInstrInfo class that is common |
| Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 12 | /// to all AMD GPUs. |
| 13 | // |
| 14 | //===----------------------------------------------------------------------===// |
| 15 | |
| Matt Arsenault | 6b6a2c3 | 2016-03-11 08:00:27 +0000 | [diff] [blame] | 16 | #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H |
| 17 | #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H |
| Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 18 | |
| Yaxun Liu | 1a14bfa | 2017-03-27 14:04:01 +0000 | [diff] [blame] | 19 | #include "AMDGPU.h" |
| Sam Kolton | a3ec5c1 | 2016-10-07 14:46:06 +0000 | [diff] [blame] | 20 | #include "Utils/AMDGPUBaseInfo.h" |
| David Blaikie | 3f833ed | 2017-11-08 01:01:31 +0000 | [diff] [blame] | 21 | #include "llvm/CodeGen/TargetInstrInfo.h" |
| Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 22 | |
| Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 23 | namespace llvm { |
| 24 | |
| Tom Stellard | 5bfbae5 | 2018-07-11 20:59:01 +0000 | [diff] [blame^] | 25 | class GCNSubtarget; |
| Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 26 | class MachineFunction; |
| 27 | class MachineInstr; |
| 28 | class MachineInstrBuilder; |
| 29 | |
| Tom Stellard | c5a154d | 2018-06-28 23:47:12 +0000 | [diff] [blame] | 30 | class AMDGPUInstrInfo { |
| Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 31 | public: |
| Tom Stellard | 5bfbae5 | 2018-07-11 20:59:01 +0000 | [diff] [blame^] | 32 | explicit AMDGPUInstrInfo(const GCNSubtarget &st); |
| Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 33 | |
| Matt Arsenault | bcf7bec | 2018-02-09 16:57:48 +0000 | [diff] [blame] | 34 | static bool isUniformMMO(const MachineMemOperand *MMO); |
| Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 35 | }; |
| Nicolai Haehnle | 5d0d303 | 2018-04-01 17:09:07 +0000 | [diff] [blame] | 36 | |
| 37 | namespace AMDGPU { |
| 38 | |
| 39 | struct RsrcIntrinsic { |
| 40 | unsigned Intr; |
| 41 | uint8_t RsrcArg; |
| 42 | bool IsImage; |
| 43 | }; |
| Nicolai Haehnle | e741d7e | 2018-06-21 13:36:33 +0000 | [diff] [blame] | 44 | const RsrcIntrinsic *lookupRsrcIntrinsic(unsigned Intr); |
| Nicolai Haehnle | 5d0d303 | 2018-04-01 17:09:07 +0000 | [diff] [blame] | 45 | |
| Nicolai Haehnle | 2f5a738 | 2018-04-04 10:58:54 +0000 | [diff] [blame] | 46 | struct D16ImageDimIntrinsic { |
| 47 | unsigned Intr; |
| 48 | unsigned D16HelperIntr; |
| 49 | }; |
| Nicolai Haehnle | e741d7e | 2018-06-21 13:36:33 +0000 | [diff] [blame] | 50 | const D16ImageDimIntrinsic *lookupD16ImageDimIntrinsic(unsigned Intr); |
| Nicolai Haehnle | 2f5a738 | 2018-04-04 10:58:54 +0000 | [diff] [blame] | 51 | |
| Nicolai Haehnle | 7a9c03f | 2018-06-21 13:36:57 +0000 | [diff] [blame] | 52 | struct ImageDimIntrinsicInfo { |
| 53 | unsigned Intr; |
| 54 | unsigned BaseOpcode; |
| 55 | MIMGDim Dim; |
| 56 | }; |
| 57 | const ImageDimIntrinsicInfo *getImageDimIntrinsicInfo(unsigned Intr); |
| 58 | |
| Nicolai Haehnle | 5d0d303 | 2018-04-01 17:09:07 +0000 | [diff] [blame] | 59 | } // end AMDGPU namespace |
| Alexander Kornienko | f00654e | 2015-06-23 09:49:53 +0000 | [diff] [blame] | 60 | } // End llvm namespace |
| Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 61 | |
| Benjamin Kramer | a7c40ef | 2014-08-13 16:26:38 +0000 | [diff] [blame] | 62 | #endif |