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Andrea Di Biagio3a6b0922018-03-08 13:05:02 +00001//===--------------------- Backend.cpp --------------------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9/// \file
10///
11/// Implementation of class Backend which emulates an hardware OoO backend.
12///
13//===----------------------------------------------------------------------===//
14
15#include "Backend.h"
16#include "HWEventListener.h"
17#include "llvm/CodeGen/TargetSchedule.h"
18#include "llvm/Support/Debug.h"
19
20namespace mca {
21
22#define DEBUG_TYPE "llvm-mca"
23
24using namespace llvm;
25
26void Backend::addEventListener(HWEventListener *Listener) {
27 if (Listener)
28 Listeners.insert(Listener);
29}
30
31void Backend::runCycle(unsigned Cycle) {
32 notifyCycleBegin(Cycle);
33
Andrea Di Biagio4732d43ca2018-03-14 14:57:23 +000034 while (SM.hasNext()) {
Matt Davis21a8d322018-05-07 18:29:15 +000035 SourceRef SR = SM.peekNext();
36 std::unique_ptr<Instruction> NewIS = IB.createInstruction(*SR.second);
Andrea Di Biagio4732d43ca2018-03-14 14:57:23 +000037 const InstrDesc &Desc = NewIS->getDesc();
Andrea Di Biagio4732d43ca2018-03-14 14:57:23 +000038 Instruction *IS = NewIS.get();
Matt Davis21a8d322018-05-07 18:29:15 +000039 InstRef IR(SR.first, IS);
40 if (!DU->isAvailable(Desc.NumMicroOps) || !DU->canDispatch(IR))
41 break;
42 Instructions[SR.first] = std::move(NewIS);
43 DU->dispatch(IR, STI);
Andrea Di Biagio4732d43ca2018-03-14 14:57:23 +000044 SM.updateNext();
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +000045 }
46
47 notifyCycleEnd(Cycle);
48}
49
50void Backend::notifyCycleBegin(unsigned Cycle) {
Nicola Zaghend34e60c2018-05-14 12:53:11 +000051 LLVM_DEBUG(dbgs() << "[E] Cycle begin: " << Cycle << '\n');
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +000052 for (HWEventListener *Listener : Listeners)
Andrea Di Biagio3e646442018-04-12 10:49:40 +000053 Listener->onCycleBegin();
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +000054
Andrea Di Biagio3e646442018-04-12 10:49:40 +000055 DU->cycleEvent();
56 HWS->cycleEvent();
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +000057}
58
Clement Courbet844f22d2018-03-13 13:11:01 +000059void Backend::notifyInstructionEvent(const HWInstructionEvent &Event) {
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +000060 for (HWEventListener *Listener : Listeners)
Clement Courbet844f22d2018-03-13 13:11:01 +000061 Listener->onInstructionEvent(Event);
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +000062}
63
Andrea Di Biagio91ab2ee2018-03-19 13:23:07 +000064void Backend::notifyStallEvent(const HWStallEvent &Event) {
65 for (HWEventListener *Listener : Listeners)
66 Listener->onStallEvent(Event);
67}
68
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +000069void Backend::notifyResourceAvailable(const ResourceRef &RR) {
Nicola Zaghend34e60c2018-05-14 12:53:11 +000070 LLVM_DEBUG(dbgs() << "[E] Resource Available: [" << RR.first << '.'
71 << RR.second << "]\n");
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +000072 for (HWEventListener *Listener : Listeners)
73 Listener->onResourceAvailable(RR);
74}
75
Andrea Di Biagioa3f2e482018-03-20 18:20:39 +000076void Backend::notifyReservedBuffers(ArrayRef<unsigned> Buffers) {
77 for (HWEventListener *Listener : Listeners)
78 Listener->onReservedBuffers(Buffers);
79}
80
81void Backend::notifyReleasedBuffers(ArrayRef<unsigned> Buffers) {
82 for (HWEventListener *Listener : Listeners)
83 Listener->onReleasedBuffers(Buffers);
84}
85
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +000086void Backend::notifyCycleEnd(unsigned Cycle) {
Nicola Zaghend34e60c2018-05-14 12:53:11 +000087 LLVM_DEBUG(dbgs() << "[E] Cycle end: " << Cycle << "\n\n");
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +000088 for (HWEventListener *Listener : Listeners)
Andrea Di Biagio3e646442018-04-12 10:49:40 +000089 Listener->onCycleEnd();
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +000090}
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +000091} // namespace mca.