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gerrit-public.fairphone.software / toolchain / llvm-project / 64dfcacd5fb03908ad2432973975ebb1d3eff11f / . / llvm / lib / Target / Alpha / AlphaInstrInfo.h
blob: 182aa32f447ae01ee1cfe7d4abde3f2ac6272862 [file] [log] [blame]
Misha Brukman076b9f42005-02-04 20:25:52 +0000[diff] [blame]1//===- AlphaInstrInfo.h - Alpha Instruction Information ---------*- C++ -*-===//
Misha Brukman89b8c8d2005-04-21 23:13:11 +0000[diff] [blame]2//
Andrew Lenhartha1b5ca22005-01-22 23:41:55 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukman89b8c8d2005-04-21 23:13:11 +0000[diff] [blame]7//
Andrew Lenhartha1b5ca22005-01-22 23:41:55 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
9//
10// This file contains the Alpha implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ALPHAINSTRUCTIONINFO_H
15#define ALPHAINSTRUCTIONINFO_H
16
17#include "llvm/Target/TargetInstrInfo.h"
18#include "AlphaRegisterInfo.h"
19
20namespace llvm {
21
Chris Lattner25568e42008-01-01 01:03:04 +0000[diff] [blame]22class AlphaInstrInfo : public TargetInstrInfoImpl {
Andrew Lenhartha1b5ca22005-01-22 23:41:55 +0000[diff] [blame]23 const AlphaRegisterInfo RI;
24public:
25 AlphaInstrInfo();
26
27 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
28 /// such, whenever a client has an instance of instruction info, it should
29 /// always be able to get register info as well (through this method).
30 ///
Dan Gohmaneabd6472008-05-14 01:58:56 +0000[diff] [blame]31 virtual const AlphaRegisterInfo &getRegisterInfo() const { return RI; }
Andrew Lenhartha1b5ca22005-01-22 23:41:55 +0000[diff] [blame]32
Evan Chengc544cb02009-01-20 19:12:24 +0000[diff] [blame]33 /// Return true if the instruction is a register to register move and return
34 /// the source and dest operands and their sub-register indices by reference.
Andrew Lenhartha1b5ca22005-01-22 23:41:55 +0000[diff] [blame]35 virtual bool isMoveInstr(const MachineInstr &MI,
Evan Chengc544cb02009-01-20 19:12:24 +0000[diff] [blame]36 unsigned &SrcReg, unsigned &DstReg,
37 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]38
Dan Gohman0b273252008-11-18 19:49:32 +0000[diff] [blame]39 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
40 int &FrameIndex) const;
41 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
42 int &FrameIndex) const;
Chris Lattner042d5622006-10-24 16:41:36 +0000[diff] [blame]43
Evan Cheng99be49d2007-05-18 00:05:48 +0000[diff] [blame]44 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
Chris Lattner042d5622006-10-24 16:41:36 +0000[diff] [blame]45 MachineBasicBlock *FBB,
Owen Anderson4f6bf042008-08-14 22:49:33 +0000[diff] [blame]46 const SmallVectorImpl<MachineOperand> &Cond) const;
Owen Anderson27fb3dc2008-08-26 18:03:31 +0000[diff] [blame]47 virtual bool copyRegToReg(MachineBasicBlock &MBB,
Owen Anderson7a73ae92007-12-31 06:32:00 +0000[diff] [blame]48 MachineBasicBlock::iterator MI,
49 unsigned DestReg, unsigned SrcReg,
50 const TargetRegisterClass *DestRC,
51 const TargetRegisterClass *SrcRC) const;
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]52 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
53 MachineBasicBlock::iterator MBBI,
54 unsigned SrcReg, bool isKill, int FrameIndex,
55 const TargetRegisterClass *RC) const;
56
57 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
58 SmallVectorImpl<MachineOperand> &Addr,
59 const TargetRegisterClass *RC,
60 SmallVectorImpl<MachineInstr*> &NewMIs) const;
61
62 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
63 MachineBasicBlock::iterator MBBI,
64 unsigned DestReg, int FrameIndex,
65 const TargetRegisterClass *RC) const;
66
67 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
68 SmallVectorImpl<MachineOperand> &Addr,
69 const TargetRegisterClass *RC,
70 SmallVectorImpl<MachineInstr*> &NewMIs) const;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]71
Dan Gohman3f86b512008-12-03 18:43:12 +0000[diff] [blame]72 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
73 MachineInstr* MI,
74 const SmallVectorImpl<unsigned> &Ops,
75 int FrameIndex) const;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]76
Dan Gohman3f86b512008-12-03 18:43:12 +0000[diff] [blame]77 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
78 MachineInstr* MI,
79 const SmallVectorImpl<unsigned> &Ops,
80 MachineInstr* LoadMI) const {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]81 return 0;
82 }
83
Andrew Lenharth692e4152006-10-31 16:49:55 +0000[diff] [blame]84 bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
85 MachineBasicBlock *&FBB,
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame^]86 SmallVectorImpl<MachineOperand> &Cond,
87 bool AllowModify) const;
Evan Cheng99be49d2007-05-18 00:05:48 +0000[diff] [blame]88 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
Andrew Lenharth692e4152006-10-31 16:49:55 +0000[diff] [blame]89 void insertNoop(MachineBasicBlock &MBB,
90 MachineBasicBlock::iterator MI) const;
Dan Gohman33332bc2008-10-16 01:49:15 +0000[diff] [blame]91 bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
Owen Anderson4f6bf042008-08-14 22:49:33 +0000[diff] [blame]92 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
Andrew Lenhartha1b5ca22005-01-22 23:41:55 +0000[diff] [blame]93};
94
95}
96
97#endif