Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / 64ecca90d4290f670b58111cc46e63b3aa9b72f5 / . / llvm / lib / Target / AMDGPU / AMDGPULegalizerInfo.h
blob: f49d109b8f88afb5401c35cc9651811b6015da09 [file] [log] [blame]
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]1//===- AMDGPULegalizerInfo ---------------------------------------*- C++ -*-==//
2//
Chandler Carruth2946cd72019-01-19 08:50:56 +0000[diff] [blame]3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the targeting of the Machinelegalizer class for
10/// AMDGPU.
11/// \todo This should be generated by TableGen.
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
15#define LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
16
17#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
Matt Arsenaulte2c86cc2019-07-01 18:45:36 +0000[diff] [blame]18#include "AMDGPUArgumentUsageInfo.h"
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]19
20namespace llvm {
21
Matt Arsenaultc3fe46b2018-03-08 16:24:16 +0000[diff] [blame]22class GCNTargetMachine;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]23class LLVMContext;
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]24class GCNSubtarget;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]25
26/// This class provides the information for the target register banks.
27class AMDGPULegalizerInfo : public LegalizerInfo {
Matt Arsenault9e8e8c62019-07-01 18:49:01 +0000[diff] [blame]28 const GCNSubtarget &ST;
29
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]30public:
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]31 AMDGPULegalizerInfo(const GCNSubtarget &ST,
Matt Arsenaultc3fe46b2018-03-08 16:24:16 +0000[diff] [blame]32 const GCNTargetMachine &TM);
Matt Arsenaulta8b43392019-02-08 02:40:47 +0000[diff] [blame]33
34 bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
35 MachineIRBuilder &MIRBuilder,
36 GISelChangeObserver &Observer) const override;
37
Matt Arsenault1178dc32019-06-28 01:16:46 +0000[diff] [blame]38 Register getSegmentAperture(unsigned AddrSpace,
Matt Arsenaulta8b43392019-02-08 02:40:47 +0000[diff] [blame]39 MachineRegisterInfo &MRI,
40 MachineIRBuilder &MIRBuilder) const;
41
42 bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
43 MachineIRBuilder &MIRBuilder) const;
Matt Arsenault6aafc5e2019-05-17 12:19:57 +0000[diff] [blame]44 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
45 MachineIRBuilder &MIRBuilder) const;
Matt Arsenaulta510b572019-05-17 12:20:05 +0000[diff] [blame]46 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
47 MachineIRBuilder &MIRBuilder) const;
Matt Arsenault6aebcd52019-05-17 12:20:01 +0000[diff] [blame]48 bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
49 MachineIRBuilder &MIRBuilder) const;
Matt Arsenault2f292202019-05-17 23:05:18 +0000[diff] [blame]50 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
51 MachineIRBuilder &MIRBuilder, bool Signed) const;
Matt Arsenault6ce1b4f2019-07-10 16:31:19 +0000[diff] [blame]52 bool legalizeMinNumMaxNum(MachineInstr &MI, MachineRegisterInfo &MRI,
53 MachineIRBuilder &MIRBuilder) const;
Matt Arsenaultb0e04c02019-07-15 19:40:59 +0000[diff] [blame]54 bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
55 MachineIRBuilder &MIRBuilder) const;
Matt Arsenault6ed315f2019-07-15 19:43:04 +0000[diff] [blame]56 bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
57 MachineIRBuilder &MIRBuilder) const;
Matt Arsenaultcbd17822019-08-29 20:06:48 +0000[diff] [blame]58 bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
59 MachineIRBuilder &MIRBuilder) const;
Matt Arsenaulte15770a2019-07-01 18:40:23 +0000[diff] [blame]60
Matt Arsenault64ecca92019-09-09 17:13:44 +0000[diff] [blame^]61 bool legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI,
62 MachineIRBuilder &MIRBuilder) const;
63
Matt Arsenaulte2c86cc2019-07-01 18:45:36 +0000[diff] [blame]64 Register getLiveInRegister(MachineRegisterInfo &MRI,
65 Register Reg, LLT Ty) const;
66
67 bool loadInputValue(Register DstReg, MachineIRBuilder &B,
68 const ArgDescriptor *Arg) const;
69 bool legalizePreloadedArgIntrin(
70 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B,
71 AMDGPUFunctionArgInfo::PreloadedValue ArgType) const;
72
Austin Kerbowc99f62e2019-07-30 18:49:16 +0000[diff] [blame]73 bool legalizeFDIVFast(MachineInstr &MI, MachineRegisterInfo &MRI,
74 MachineIRBuilder &B) const;
75
Matt Arsenault9e8e8c62019-07-01 18:49:01 +0000[diff] [blame]76 bool legalizeImplicitArgPtr(MachineInstr &MI, MachineRegisterInfo &MRI,
77 MachineIRBuilder &B) const;
Matt Arsenaultf581d572019-09-05 02:20:39 +0000[diff] [blame]78 bool legalizeIsAddrSpace(MachineInstr &MI, MachineRegisterInfo &MRI,
79 MachineIRBuilder &B, unsigned AddrSpace) const;
Matt Arsenaulte15770a2019-07-01 18:40:23 +0000[diff] [blame]80 bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
81 MachineIRBuilder &MIRBuilder) const override;
82
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]83};
84} // End llvm namespace.
85#endif