Matt Arsenault | 657f871 | 2016-07-12 19:01:23 +0000 | [diff] [blame^] | 1 | ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s |
| 2 | |
| 3 | ; CHECK-LABEL: {{^}}test_kill_depth_0_imm_pos: |
| 4 | ; CHECK-NEXT: ; BB#0: |
| 5 | ; CHECK-NEXT: s_endpgm |
| 6 | define amdgpu_ps void @test_kill_depth_0_imm_pos() #0 { |
| 7 | call void @llvm.AMDGPU.kill(float 0.0) |
| 8 | ret void |
| 9 | } |
| 10 | |
| 11 | ; CHECK-LABEL: {{^}}test_kill_depth_0_imm_neg: |
| 12 | ; CHECK-NEXT: ; BB#0: |
| 13 | ; CHECK-NEXT: s_mov_b64 exec, 0 |
| 14 | ; CHECK-NEXT: s_endpgm |
| 15 | define amdgpu_ps void @test_kill_depth_0_imm_neg() #0 { |
| 16 | call void @llvm.AMDGPU.kill(float -0.0) |
| 17 | ret void |
| 18 | } |
| 19 | |
| 20 | ; CHECK-LABEL: {{^}}test_kill_depth_var: |
| 21 | ; CHECK-NEXT: ; BB#0: |
| 22 | ; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v0 |
| 23 | ; CHECK-NEXT: s_endpgm |
| 24 | define amdgpu_ps void @test_kill_depth_var(float %x) #0 { |
| 25 | call void @llvm.AMDGPU.kill(float %x) |
| 26 | ret void |
| 27 | } |
| 28 | |
| 29 | ; FIXME: why does the skip depend on the asm length in the same block? |
| 30 | |
| 31 | ; CHECK-LABEL: {{^}}test_kill_control_flow: |
| 32 | ; CHECK: s_cmp_lg_i32 s{{[0-9]+}}, 0 |
| 33 | ; CHECK: s_cbranch_scc1 [[RETURN_BB:BB[0-9]+_[0-9]+]] |
| 34 | |
| 35 | ; CHECK: ; BB#1: |
| 36 | ; CHECK: v_nop_e64 |
| 37 | ; CHECK: v_nop_e64 |
| 38 | ; CHECK: v_nop_e64 |
| 39 | ; CHECK: v_nop_e64 |
| 40 | ; CHECK: v_nop_e64 |
| 41 | ; CHECK: v_nop_e64 |
| 42 | ; CHECK: v_nop_e64 |
| 43 | ; CHECK: v_nop_e64 |
| 44 | ; CHECK: v_nop_e64 |
| 45 | ; CHECK: v_nop_e64 |
| 46 | |
| 47 | ; CHECK: s_cbranch_execnz [[SPLIT_BB:BB[0-9]+_[0-9]+]] |
| 48 | ; CHECK-NEXT: ; BB#3: |
| 49 | ; CHECK-NEXT: exp 0, 9, 0, 1, 1, v0, v0, v0, v0 |
| 50 | ; CHECK-NEXT: s_endpgm |
| 51 | |
| 52 | ; CHECK-NEXT: {{^}}[[SPLIT_BB]]: |
| 53 | ; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v7 |
| 54 | ; CHECK-NEXT: {{^}}BB{{[0-9]+_[0-9]+}}: |
| 55 | ; CHECK-NEXT: s_endpgm |
| 56 | define amdgpu_ps void @test_kill_control_flow(i32 inreg %arg) #0 { |
| 57 | entry: |
| 58 | %cmp = icmp eq i32 %arg, 0 |
| 59 | br i1 %cmp, label %bb, label %exit |
| 60 | |
| 61 | bb: |
| 62 | %var = call float asm sideeffect " |
| 63 | v_mov_b32_e64 v7, -1 |
| 64 | v_nop_e64 |
| 65 | v_nop_e64 |
| 66 | v_nop_e64 |
| 67 | v_nop_e64 |
| 68 | v_nop_e64 |
| 69 | v_nop_e64 |
| 70 | v_nop_e64 |
| 71 | v_nop_e64 |
| 72 | v_nop_e64 |
| 73 | v_nop_e64", "={VGPR7}"() |
| 74 | call void @llvm.AMDGPU.kill(float %var) |
| 75 | br label %exit |
| 76 | |
| 77 | exit: |
| 78 | ret void |
| 79 | } |
| 80 | |
| 81 | ; CHECK-LABEL: {{^}}test_kill_control_flow_remainder: |
| 82 | ; CHECK: s_cmp_lg_i32 s{{[0-9]+}}, 0 |
| 83 | ; CHECK-NEXT: s_cbranch_scc1 [[RETURN_BB:BB[0-9]+_[0-9]+]] |
| 84 | |
| 85 | ; CHECK-NEXT: ; BB#1: ; %bb |
| 86 | ; CHECK: v_mov_b32_e64 v7, -1 |
| 87 | ; CHECK: v_nop_e64 |
| 88 | ; CHECK: v_nop_e64 |
| 89 | ; CHECK: v_nop_e64 |
| 90 | ; CHECK: v_nop_e64 |
| 91 | ; CHECK: v_nop_e64 |
| 92 | ; CHECK: v_nop_e64 |
| 93 | ; CHECK: v_nop_e64 |
| 94 | ; CHECK: v_nop_e64 |
| 95 | ; CHECK: ;;#ASMEND |
| 96 | ; CHECK: v_mov_b32_e64 v8, -1 |
| 97 | ; CHECK: ;;#ASMEND |
| 98 | ; CHECK-NEXT: s_cbranch_execnz [[SPLIT_BB:BB[0-9]+_[0-9]+]] |
| 99 | |
| 100 | ; CHECK-NEXT: ; BB#3: |
| 101 | ; CHECK-NEXT: exp 0, 9, 0, 1, 1, v0, v0, v0, v0 |
| 102 | ; CHECK-NEXT: s_endpgm |
| 103 | |
| 104 | ; CHECK-NEXT: {{^}}[[SPLIT_BB]]: |
| 105 | ; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v7 |
| 106 | ; CHECK: buffer_store_dword v8 |
| 107 | ; CHECK: v_mov_b32_e64 v9, -2 |
| 108 | |
| 109 | ; CHECK: {{^}}BB{{[0-9]+_[0-9]+}}: |
| 110 | ; CHECK: buffer_store_dword v9 |
| 111 | ; CHECK-NEXT: s_endpgm |
| 112 | define amdgpu_ps void @test_kill_control_flow_remainder(i32 inreg %arg) #0 { |
| 113 | entry: |
| 114 | %cmp = icmp eq i32 %arg, 0 |
| 115 | br i1 %cmp, label %bb, label %exit |
| 116 | |
| 117 | bb: |
| 118 | %var = call float asm sideeffect " |
| 119 | v_mov_b32_e64 v7, -1 |
| 120 | v_nop_e64 |
| 121 | v_nop_e64 |
| 122 | v_nop_e64 |
| 123 | v_nop_e64 |
| 124 | v_nop_e64 |
| 125 | v_nop_e64 |
| 126 | v_nop_e64 |
| 127 | v_nop_e64 |
| 128 | v_nop_e64 |
| 129 | v_nop_e64 |
| 130 | v_nop_e64", "={VGPR7}"() |
| 131 | %live.across = call float asm sideeffect "v_mov_b32_e64 v8, -1", "={VGPR8}"() |
| 132 | call void @llvm.AMDGPU.kill(float %var) |
| 133 | store volatile float %live.across, float addrspace(1)* undef |
| 134 | %live.out = call float asm sideeffect "v_mov_b32_e64 v9, -2", "={VGPR9}"() |
| 135 | br label %exit |
| 136 | |
| 137 | exit: |
| 138 | %phi = phi float [ 0.0, %entry ], [ %live.out, %bb ] |
| 139 | store float %phi, float addrspace(1)* undef |
| 140 | ret void |
| 141 | } |
| 142 | |
| 143 | declare void @llvm.AMDGPU.kill(float) #0 |
| 144 | |
| 145 | attributes #0 = { nounwind } |