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gerrit-public.fairphone.software / toolchain / llvm-project / 775bb7437932ea6141c33ab63074640fb541997e / . / llvm / test / CodeGen / RISCV / mul.ll
blob: 2eb5db79d1b7d2cb13541a015d70d2730f5de3b9 [file] [log] [blame]
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN: | FileCheck %s -check-prefix=RV32I
4
5define i32 @square(i32 %a) {
6; RV32I-LABEL: square:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7; RV32I: # %bb.0:
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]8; RV32I-NEXT: sw ra, 12(s0)
9; RV32I-NEXT: lui a1, %hi(__mulsi3)
10; RV32I-NEXT: addi a2, a1, %lo(__mulsi3)
11; RV32I-NEXT: addi a1, a0, 0
12; RV32I-NEXT: jalr ra, a2, 0
13; RV32I-NEXT: lw ra, 12(s0)
14; RV32I-NEXT: jalr zero, ra, 0
15 %1 = mul i32 %a, %a
16 ret i32 %1
17}
18
19define i32 @mul(i32 %a, i32 %b) {
20; RV32I-LABEL: mul:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]21; RV32I: # %bb.0:
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]22; RV32I-NEXT: sw ra, 12(s0)
23; RV32I-NEXT: lui a2, %hi(__mulsi3)
24; RV32I-NEXT: addi a2, a2, %lo(__mulsi3)
25; RV32I-NEXT: jalr ra, a2, 0
26; RV32I-NEXT: lw ra, 12(s0)
27; RV32I-NEXT: jalr zero, ra, 0
28 %1 = mul i32 %a, %b
29 ret i32 %1
30}
31
32define i32 @mul_constant(i32 %a) {
33; RV32I-LABEL: mul_constant:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]34; RV32I: # %bb.0:
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]35; RV32I-NEXT: sw ra, 12(s0)
36; RV32I-NEXT: lui a1, %hi(__mulsi3)
37; RV32I-NEXT: addi a2, a1, %lo(__mulsi3)
38; RV32I-NEXT: addi a1, zero, 5
39; RV32I-NEXT: jalr ra, a2, 0
40; RV32I-NEXT: lw ra, 12(s0)
41; RV32I-NEXT: jalr zero, ra, 0
42 %1 = mul i32 %a, 5
43 ret i32 %1
44}
45
46define i32 @mul_pow2(i32 %a) {
47; RV32I-LABEL: mul_pow2:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]48; RV32I: # %bb.0:
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]49; RV32I-NEXT: slli a0, a0, 3
50; RV32I-NEXT: jalr zero, ra, 0
51 %1 = mul i32 %a, 8
52 ret i32 %1
53}
54
55define i64 @mul64(i64 %a, i64 %b) {
56; RV32I-LABEL: mul64:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]57; RV32I: # %bb.0:
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]58; RV32I-NEXT: sw ra, 12(s0)
59; RV32I-NEXT: lui a4, %hi(__muldi3)
60; RV32I-NEXT: addi a4, a4, %lo(__muldi3)
61; RV32I-NEXT: jalr ra, a4, 0
62; RV32I-NEXT: lw ra, 12(s0)
63; RV32I-NEXT: jalr zero, ra, 0
64 %1 = mul i64 %a, %b
65 ret i64 %1
66}
67
68define i64 @mul64_constant(i64 %a) {
69; RV32I-LABEL: mul64_constant:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]70; RV32I: # %bb.0:
Alex Bradburyffc435e2017-11-21 08:11:03 +0000[diff] [blame]71; RV32I-NEXT: sw ra, 12(s0)
72; RV32I-NEXT: lui a2, %hi(__muldi3)
73; RV32I-NEXT: addi a4, a2, %lo(__muldi3)
74; RV32I-NEXT: addi a2, zero, 5
75; RV32I-NEXT: addi a3, zero, 0
76; RV32I-NEXT: jalr ra, a4, 0
77; RV32I-NEXT: lw ra, 12(s0)
78; RV32I-NEXT: jalr zero, ra, 0
79 %1 = mul i64 %a, 5
80 ret i64 %1
81}