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gerrit-public.fairphone.software / toolchain / llvm-project / 66c36b814f7ab00005fc98adc6a6592e4c958057 / . / llvm / test / CodeGen / AArch64 / atomic-ops.ll
blob: f8db05fd416ea557a4a89f72c180ff5019382374 [file] [log] [blame]
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]1; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
Kevin Qin07334d32014-02-21 07:45:48 +0000[diff] [blame]2; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-REG %s
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]3; RUN: llc -mtriple=arm64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM64
4; RUN: llc -mtriple=arm64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-REG
5
6
7; Point of CHECK-REG is to make sure UNPREDICTABLE instructions aren't created
8; (i.e. reusing a register for status & data in store exclusive).
9; CHECK-REG-NOT: stlxrb w[[NEW:[0-9]+]], w[[NEW]], [x{{[0-9]+}}]
10; CHECK-REG-NOT: stlxrb w[[NEW:[0-9]+]], x[[NEW]], [x{{[0-9]+}}]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]11
12@var8 = global i8 0
13@var16 = global i16 0
14@var32 = global i32 0
15@var64 = global i64 0
16
17define i8 @test_atomic_load_add_i8(i8 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]18; CHECK-LABEL: test_atomic_load_add_i8:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]19 %old = atomicrmw add i8* @var8, i8 %offset seq_cst
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]20; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]21; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]22; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]23
24; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]25; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]26 ; w0 below is a reasonable guess but could change: it certainly comes into the
27 ; function there.
28; CHECK-NEXT: add [[NEW:w[0-9]+]], w[[OLD]], w0
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]29; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]30; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]31; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]32
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]33; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]34 ret i8 %old
35}
36
37define i16 @test_atomic_load_add_i16(i16 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]38; CHECK-LABEL: test_atomic_load_add_i16:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]39 %old = atomicrmw add i16* @var16, i16 %offset acquire
40; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]41; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]42; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]43
44; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]45; ; CHECK: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]46 ; w0 below is a reasonable guess but could change: it certainly comes into the
47 ; function there.
48; CHECK-NEXT: add [[NEW:w[0-9]+]], w[[OLD]], w0
49; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]50; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]51; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]52
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]53; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]54 ret i16 %old
55}
56
57define i32 @test_atomic_load_add_i32(i32 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]58; CHECK-LABEL: test_atomic_load_add_i32:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]59 %old = atomicrmw add i32* @var32, i32 %offset release
60; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]61; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]62; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]63
64; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]65; ; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]66 ; w0 below is a reasonable guess but could change: it certainly comes into the
67 ; function there.
68; CHECK-NEXT: add [[NEW:w[0-9]+]], w[[OLD]], w0
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]69; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]70; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]71; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]72
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]73; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]74 ret i32 %old
75}
76
77define i64 @test_atomic_load_add_i64(i64 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]78; CHECK-LABEL: test_atomic_load_add_i64:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]79 %old = atomicrmw add i64* @var64, i64 %offset monotonic
80; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]81; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]82; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]83
84; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]85; ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]86 ; x0 below is a reasonable guess but could change: it certainly comes into the
87 ; function there.
88; CHECK-NEXT: add [[NEW:x[0-9]+]], x[[OLD]], x0
89; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]90; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]91; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]92
93; CHECK: mov x0, x[[OLD]]
94 ret i64 %old
95}
96
97define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]98; CHECK-LABEL: test_atomic_load_sub_i8:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]99 %old = atomicrmw sub i8* @var8, i8 %offset monotonic
100; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]101; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]102; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]103
104; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]105; ; CHECK: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]106 ; w0 below is a reasonable guess but could change: it certainly comes into the
107 ; function there.
108; CHECK-NEXT: sub [[NEW:w[0-9]+]], w[[OLD]], w0
109; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]110; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]111; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]112
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]113; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]114 ret i8 %old
115}
116
117define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]118; CHECK-LABEL: test_atomic_load_sub_i16:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]119 %old = atomicrmw sub i16* @var16, i16 %offset release
120; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]121; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]122; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]123
124; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]125; ; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]126 ; w0 below is a reasonable guess but could change: it certainly comes into the
127 ; function there.
128; CHECK-NEXT: sub [[NEW:w[0-9]+]], w[[OLD]], w0
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]129; CHECK-NEXT: stlxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]130; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]131; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]132
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]133; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]134 ret i16 %old
135}
136
137define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]138; CHECK-LABEL: test_atomic_load_sub_i32:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]139 %old = atomicrmw sub i32* @var32, i32 %offset acquire
140; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]141; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]142; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]143
144; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]145; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]146 ; w0 below is a reasonable guess but could change: it certainly comes into the
147 ; function there.
148; CHECK-NEXT: sub [[NEW:w[0-9]+]], w[[OLD]], w0
149; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]150; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]151; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]152
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]153; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]154 ret i32 %old
155}
156
157define i64 @test_atomic_load_sub_i64(i64 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]158; CHECK-LABEL: test_atomic_load_sub_i64:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]159 %old = atomicrmw sub i64* @var64, i64 %offset seq_cst
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]160; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]161; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]162; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]163
164; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]165; ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]166 ; x0 below is a reasonable guess but could change: it certainly comes into the
167 ; function there.
168; CHECK-NEXT: sub [[NEW:x[0-9]+]], x[[OLD]], x0
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]169; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]170; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]171; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]172
173; CHECK: mov x0, x[[OLD]]
174 ret i64 %old
175}
176
177define i8 @test_atomic_load_and_i8(i8 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]178; CHECK-LABEL: test_atomic_load_and_i8:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]179 %old = atomicrmw and i8* @var8, i8 %offset release
180; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]181; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]182; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]183
184; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]185; ; CHECK: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]186 ; w0 below is a reasonable guess but could change: it certainly comes into the
187 ; function there.
188; CHECK-NEXT: and [[NEW:w[0-9]+]], w[[OLD]], w0
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]189; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]190; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]191; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]192
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]193; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]194 ret i8 %old
195}
196
197define i16 @test_atomic_load_and_i16(i16 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]198; CHECK-LABEL: test_atomic_load_and_i16:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]199 %old = atomicrmw and i16* @var16, i16 %offset monotonic
200; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]201; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]202; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]203
204; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]205; ; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]206 ; w0 below is a reasonable guess but could change: it certainly comes into the
207 ; function there.
208; CHECK-NEXT: and [[NEW:w[0-9]+]], w[[OLD]], w0
209; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]210; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]211; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]212
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]213; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]214 ret i16 %old
215}
216
217define i32 @test_atomic_load_and_i32(i32 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]218; CHECK-LABEL: test_atomic_load_and_i32:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]219 %old = atomicrmw and i32* @var32, i32 %offset seq_cst
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]220; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]221; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]222; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]223
224; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]225; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]226 ; w0 below is a reasonable guess but could change: it certainly comes into the
227 ; function there.
228; CHECK-NEXT: and [[NEW:w[0-9]+]], w[[OLD]], w0
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]229; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]230; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]231; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]232
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]233; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]234 ret i32 %old
235}
236
237define i64 @test_atomic_load_and_i64(i64 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]238; CHECK-LABEL: test_atomic_load_and_i64:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]239 %old = atomicrmw and i64* @var64, i64 %offset acquire
240; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]241; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]242; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]243
244; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]245; ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]246 ; x0 below is a reasonable guess but could change: it certainly comes into the
247 ; function there.
248; CHECK-NEXT: and [[NEW:x[0-9]+]], x[[OLD]], x0
249; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]250; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]251; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]252
253; CHECK: mov x0, x[[OLD]]
254 ret i64 %old
255}
256
257define i8 @test_atomic_load_or_i8(i8 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]258; CHECK-LABEL: test_atomic_load_or_i8:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]259 %old = atomicrmw or i8* @var8, i8 %offset seq_cst
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]260; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]261; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]262; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]263
264; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]265; ; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]266 ; w0 below is a reasonable guess but could change: it certainly comes into the
267 ; function there.
268; CHECK-NEXT: orr [[NEW:w[0-9]+]], w[[OLD]], w0
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]269; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]270; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]271; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]272
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]273; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]274 ret i8 %old
275}
276
277define i16 @test_atomic_load_or_i16(i16 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]278; CHECK-LABEL: test_atomic_load_or_i16:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]279 %old = atomicrmw or i16* @var16, i16 %offset monotonic
280; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]281; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]282; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]283
284; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]285; ; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]286 ; w0 below is a reasonable guess but could change: it certainly comes into the
287 ; function there.
288; CHECK-NEXT: orr [[NEW:w[0-9]+]], w[[OLD]], w0
289; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]290; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]291; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]292
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]293; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]294 ret i16 %old
295}
296
297define i32 @test_atomic_load_or_i32(i32 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]298; CHECK-LABEL: test_atomic_load_or_i32:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]299 %old = atomicrmw or i32* @var32, i32 %offset acquire
300; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]301; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]302; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]303
304; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]305; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]306 ; w0 below is a reasonable guess but could change: it certainly comes into the
307 ; function there.
308; CHECK-NEXT: orr [[NEW:w[0-9]+]], w[[OLD]], w0
309; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]310; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]311; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]312
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]313; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]314 ret i32 %old
315}
316
317define i64 @test_atomic_load_or_i64(i64 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]318; CHECK-LABEL: test_atomic_load_or_i64:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]319 %old = atomicrmw or i64* @var64, i64 %offset release
320; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]321; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]322; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]323
324; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]325; ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]326 ; x0 below is a reasonable guess but could change: it certainly comes into the
327 ; function there.
328; CHECK-NEXT: orr [[NEW:x[0-9]+]], x[[OLD]], x0
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]329; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]330; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]331; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]332
333; CHECK: mov x0, x[[OLD]]
334 ret i64 %old
335}
336
337define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]338; CHECK-LABEL: test_atomic_load_xor_i8:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]339 %old = atomicrmw xor i8* @var8, i8 %offset acquire
340; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]341; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]342; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]343
344; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]345; ; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]346 ; w0 below is a reasonable guess but could change: it certainly comes into the
347 ; function there.
348; CHECK-NEXT: eor [[NEW:w[0-9]+]], w[[OLD]], w0
349; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]350; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]351; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]352
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]353; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]354 ret i8 %old
355}
356
357define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]358; CHECK-LABEL: test_atomic_load_xor_i16:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]359 %old = atomicrmw xor i16* @var16, i16 %offset release
360; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]361; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]362; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]363
364; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]365; ; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]366 ; w0 below is a reasonable guess but could change: it certainly comes into the
367 ; function there.
368; CHECK-NEXT: eor [[NEW:w[0-9]+]], w[[OLD]], w0
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]369; CHECK-NEXT: stlxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]370; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]371; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]372
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]373; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]374 ret i16 %old
375}
376
377define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]378; CHECK-LABEL: test_atomic_load_xor_i32:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]379 %old = atomicrmw xor i32* @var32, i32 %offset seq_cst
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]380; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]381; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]382; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]383
384; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]385; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]386 ; w0 below is a reasonable guess but could change: it certainly comes into the
387 ; function there.
388; CHECK-NEXT: eor [[NEW:w[0-9]+]], w[[OLD]], w0
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]389; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]390; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]391; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]392
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]393; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]394 ret i32 %old
395}
396
397define i64 @test_atomic_load_xor_i64(i64 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]398; CHECK-LABEL: test_atomic_load_xor_i64:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]399 %old = atomicrmw xor i64* @var64, i64 %offset monotonic
400; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]401; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]402; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]403
404; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]405; ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]406 ; x0 below is a reasonable guess but could change: it certainly comes into the
407 ; function there.
408; CHECK-NEXT: eor [[NEW:x[0-9]+]], x[[OLD]], x0
409; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]410; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]411; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]412
413; CHECK: mov x0, x[[OLD]]
414 ret i64 %old
415}
416
417define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]418; CHECK-LABEL: test_atomic_load_xchg_i8:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]419 %old = atomicrmw xchg i8* @var8, i8 %offset monotonic
420; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]421; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]422; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]423
424; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]425; ; CHECK: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]426 ; w0 below is a reasonable guess but could change: it certainly comes into the
427 ; function there.
428; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], w0, [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]429; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]430; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]431
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]432; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]433 ret i8 %old
434}
435
436define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]437; CHECK-LABEL: test_atomic_load_xchg_i16:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]438 %old = atomicrmw xchg i16* @var16, i16 %offset seq_cst
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]439; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]440; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]441; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]442
443; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]444; ; CHECK: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]445 ; w0 below is a reasonable guess but could change: it certainly comes into the
446 ; function there.
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]447; CHECK-NEXT: stlxrh [[STATUS:w[0-9]+]], w0, [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]448; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]449; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]450
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]451; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]452 ret i16 %old
453}
454
455define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]456; CHECK-LABEL: test_atomic_load_xchg_i32:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]457 %old = atomicrmw xchg i32* @var32, i32 %offset release
458; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]459; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]460; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]461
462; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]463; ; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]464 ; w0 below is a reasonable guess but could change: it certainly comes into the
465 ; function there.
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]466; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], w0, [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]467; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]468; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]469
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]470; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]471 ret i32 %old
472}
473
474define i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]475; CHECK-LABEL: test_atomic_load_xchg_i64:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]476 %old = atomicrmw xchg i64* @var64, i64 %offset acquire
477; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]478; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]479; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]480
481; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]482; ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]483 ; x0 below is a reasonable guess but could change: it certainly comes into the
484 ; function there.
485; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], x0, [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]486; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]487; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]488
489; CHECK: mov x0, x[[OLD]]
490 ret i64 %old
491}
492
493
494define i8 @test_atomic_load_min_i8(i8 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]495; CHECK-LABEL: test_atomic_load_min_i8:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]496 %old = atomicrmw min i8* @var8, i8 %offset acquire
497; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]498; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]499; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]500
501; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]502; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]503 ; w0 below is a reasonable guess but could change: it certainly comes into the
504 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]505; CHECK-AARCH64-NEXT: cmp w0, w[[OLD]], sxtb
506; CHECK-AARCH64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt
507
508; CHECK-ARM64-NEXT: sxtb w[[OLD_EXT:[0-9]+]], w[[OLD]]
509; CHECK-ARM64-NEXT: cmp w[[OLD_EXT]], w0, sxtb
510; CHECK-ARM64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, le
511
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]512; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]513; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]514; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]515
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]516; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]517 ret i8 %old
518}
519
520define i16 @test_atomic_load_min_i16(i16 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]521; CHECK-LABEL: test_atomic_load_min_i16:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]522 %old = atomicrmw min i16* @var16, i16 %offset release
523; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]524; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]525; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]526
527; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]528; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]529 ; w0 below is a reasonable guess but could change: it certainly comes into the
530 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]531; CHECK-AARCH64-NEXT: cmp w0, w[[OLD]], sxth
532; CHECK-AARCH64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt
533
534; CHECK-ARM64-NEXT: sxth w[[OLD_EXT:[0-9]+]], w[[OLD]]
535; CHECK-ARM64-NEXT: cmp w[[OLD_EXT]], w0, sxth
536; CHECK-ARM64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, le
537
538
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]539; CHECK-NEXT: stlxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]540; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]541; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]542
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]543; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]544 ret i16 %old
545}
546
547define i32 @test_atomic_load_min_i32(i32 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]548; CHECK-LABEL: test_atomic_load_min_i32:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]549 %old = atomicrmw min i32* @var32, i32 %offset monotonic
550; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]551; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]552; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]553
554; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]555; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]556 ; w0 below is a reasonable guess but could change: it certainly comes into the
557 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]558; CHECK-AARCH64-NEXT: cmp w0, w[[OLD]]
559; CHECK-AARCH64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt
560
561; CHECK-ARM64-NEXT: cmp w[[OLD]], w0
562; CHECK-ARM64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, le
563
564
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]565; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]566; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]567; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]568
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]569; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]570 ret i32 %old
571}
572
573define i64 @test_atomic_load_min_i64(i64 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]574; CHECK-LABEL: test_atomic_load_min_i64:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]575 %old = atomicrmw min i64* @var64, i64 %offset seq_cst
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]576; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]577; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]578; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]579
580; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]581; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]582 ; x0 below is a reasonable guess but could change: it certainly comes into the
583 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]584; CHECK-AARCH64-NEXT: cmp x0, x[[OLD]]
585; CHECK-AARCH64-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, gt
586
587; CHECK-ARM64-NEXT: cmp x[[OLD]], x0
588; CHECK-ARM64-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, le
589
590
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]591; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]592; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]593; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]594
595; CHECK: mov x0, x[[OLD]]
596 ret i64 %old
597}
598
599define i8 @test_atomic_load_max_i8(i8 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]600; CHECK-LABEL: test_atomic_load_max_i8:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]601 %old = atomicrmw max i8* @var8, i8 %offset seq_cst
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]602; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]603; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]604; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]605
606; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]607; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]608 ; w0 below is a reasonable guess but could change: it certainly comes into the
609 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]610; CHECK-AARCH64-NEXT: cmp w0, w[[OLD]], sxtb
611; CHECK-AARCH64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lt
612
613; CHECK-ARM64-NEXT: sxtb w[[OLD_EXT:[0-9]+]], w[[OLD]]
614; CHECK-ARM64-NEXT: cmp w[[OLD_EXT]], w0, sxtb
615; CHECK-ARM64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt
616
617
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]618; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]619; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]620; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]621
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]622; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]623 ret i8 %old
624}
625
626define i16 @test_atomic_load_max_i16(i16 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]627; CHECK-LABEL: test_atomic_load_max_i16:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]628 %old = atomicrmw max i16* @var16, i16 %offset acquire
629; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]630; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]631; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]632
633; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]634; CHECK: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]635 ; w0 below is a reasonable guess but could change: it certainly comes into the
636 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]637; CHECK-AARCH64-NEXT: cmp w0, w[[OLD]], sxth
638; CHECK-AARCH64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lt
639
640; CHECK-ARM64-NEXT: sxth w[[OLD_EXT:[0-9]+]], w[[OLD]]
641; CHECK-ARM64-NEXT: cmp w[[OLD_EXT]], w0, sxth
642; CHECK-ARM64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt
643
644
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]645; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]646; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]647; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]648
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]649; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]650 ret i16 %old
651}
652
653define i32 @test_atomic_load_max_i32(i32 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]654; CHECK-LABEL: test_atomic_load_max_i32:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]655 %old = atomicrmw max i32* @var32, i32 %offset release
656; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]657; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]658; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]659
660; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]661; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]662 ; w0 below is a reasonable guess but could change: it certainly comes into the
663 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]664; CHECK-AARCH64-NEXT: cmp w0, w[[OLD]]
665; CHECK-AARCH64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lt
666
667; CHECK-ARM64-NEXT: cmp w[[OLD]], w0
668; CHECK-ARM64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt
669
670
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]671; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]672; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]673; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]674
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]675; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]676 ret i32 %old
677}
678
679define i64 @test_atomic_load_max_i64(i64 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]680; CHECK-LABEL: test_atomic_load_max_i64:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]681 %old = atomicrmw max i64* @var64, i64 %offset monotonic
682; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]683; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]684; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]685
686; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]687; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]688 ; x0 below is a reasonable guess but could change: it certainly comes into the
689 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]690; CHECK-AARCH64-NEXT: cmp x0, x[[OLD]]
691; CHECK-AARCH64-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, lt
692
693; CHECK-ARM64-NEXT: cmp x[[OLD]], x0
694; CHECK-ARM64-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, gt
695
696
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]697; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]698; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]699; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]700
701; CHECK: mov x0, x[[OLD]]
702 ret i64 %old
703}
704
705define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]706; CHECK-LABEL: test_atomic_load_umin_i8:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]707 %old = atomicrmw umin i8* @var8, i8 %offset monotonic
708; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]709; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]710; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]711
712; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]713; CHECK: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]714 ; w0 below is a reasonable guess but could change: it certainly comes into the
715 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]716; CHECK-AARCH64-NEXT: cmp w0, w[[OLD]], uxtb
717; CHECK-AARCH64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi
718
719; CHECK-ARM64-NEXT: cmp w[[OLD]], w0, uxtb
720; CHECK-ARM64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, ls
721
722
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]723; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]724; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]725; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]726
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]727; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]728 ret i8 %old
729}
730
731define i16 @test_atomic_load_umin_i16(i16 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]732; CHECK-LABEL: test_atomic_load_umin_i16:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]733 %old = atomicrmw umin i16* @var16, i16 %offset acquire
734; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]735; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]736; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]737
738; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]739; CHECK: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]740 ; w0 below is a reasonable guess but could change: it certainly comes into the
741 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]742; CHECK-AARCH64-NEXT: cmp w0, w[[OLD]], uxth
743; CHECK-AARCH64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi
744
745; CHECK-ARM64-NEXT: cmp w[[OLD]], w0, uxth
746; CHECK-ARM64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, ls
747
748
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]749; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]750; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]751; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]752
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]753; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]754 ret i16 %old
755}
756
757define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]758; CHECK-LABEL: test_atomic_load_umin_i32:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]759 %old = atomicrmw umin i32* @var32, i32 %offset seq_cst
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]760; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]761; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]762; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]763
764; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]765; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]766 ; w0 below is a reasonable guess but could change: it certainly comes into the
767 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]768; CHECK-AARCH64-NEXT: cmp w0, w[[OLD]]
769; CHECK-AARCH64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi
770
771; CHECK-ARM64-NEXT: cmp w[[OLD]], w0
772; CHECK-ARM64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, ls
773
774
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]775; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]776; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]777; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]778
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]779; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]780 ret i32 %old
781}
782
783define i64 @test_atomic_load_umin_i64(i64 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]784; CHECK-LABEL: test_atomic_load_umin_i64:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]785 %old = atomicrmw umin i64* @var64, i64 %offset acq_rel
786; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]787; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]788; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]789
790; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]791; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]792 ; x0 below is a reasonable guess but could change: it certainly comes into the
793 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]794; CHECK-AARCH64-NEXT: cmp x0, x[[OLD]]
795; CHECK-AARCH64-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, hi
796
797; CHECK-ARM64-NEXT: cmp x[[OLD]], x0
798; CHECK-ARM64-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, ls
799
800
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]801; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]802; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]803; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]804
805; CHECK: mov x0, x[[OLD]]
806 ret i64 %old
807}
808
809define i8 @test_atomic_load_umax_i8(i8 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]810; CHECK-LABEL: test_atomic_load_umax_i8:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]811 %old = atomicrmw umax i8* @var8, i8 %offset acq_rel
812; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]813; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]814; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]815
816; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]817; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]818 ; w0 below is a reasonable guess but could change: it certainly comes into the
819 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]820; CHECK-AARCH64-NEXT: cmp w0, w[[OLD]], uxtb
821; CHECK-AARCH64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lo
822
823; CHECK-ARM64-NEXT: cmp w[[OLD]], w0, uxtb
824; CHECK-ARM64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi
825
826
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]827; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]828; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]829; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]830
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]831; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]832 ret i8 %old
833}
834
835define i16 @test_atomic_load_umax_i16(i16 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]836; CHECK-LABEL: test_atomic_load_umax_i16:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]837 %old = atomicrmw umax i16* @var16, i16 %offset monotonic
838; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]839; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]840; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]841
842; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]843; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]844 ; w0 below is a reasonable guess but could change: it certainly comes into the
845 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]846; CHECK-AARCH64-NEXT: cmp w0, w[[OLD]], uxth
847; CHECK-AARCH64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lo
848
849; CHECK-ARM64-NEXT: cmp w[[OLD]], w0, uxth
850; CHECK-ARM64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi
851
852
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]853; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]854; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]855; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]856
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]857; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]858 ret i16 %old
859}
860
861define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]862; CHECK-LABEL: test_atomic_load_umax_i32:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]863 %old = atomicrmw umax i32* @var32, i32 %offset seq_cst
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]864; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]865; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]866; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]867
868; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]869; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]870 ; w0 below is a reasonable guess but could change: it certainly comes into the
871 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]872; CHECK-AARCH64-NEXT: cmp w0, w[[OLD]]
873; CHECK-AARCH64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lo
874
875; CHECK-ARM64-NEXT: cmp w[[OLD]], w0
876; CHECK-ARM64-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi
877
878
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]879; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]880; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]881; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]882
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]883; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]884 ret i32 %old
885}
886
887define i64 @test_atomic_load_umax_i64(i64 %offset) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]888; CHECK-LABEL: test_atomic_load_umax_i64:
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]889 %old = atomicrmw umax i64* @var64, i64 %offset release
890; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]891; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]892; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]893
894; CHECK: .LBB{{[0-9]+}}_1:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]895; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]896 ; x0 below is a reasonable guess but could change: it certainly comes into the
897 ; function there.
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]898; CHECK-AARCH64-NEXT: cmp x0, x[[OLD]]
899; CHECK-AARCH64-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, lo
900
901; CHECK-ARM64-NEXT: cmp x[[OLD]], x0
902; CHECK-ARM64-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, hi
903
904
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]905; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]906; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]907; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]908
909; CHECK: mov x0, x[[OLD]]
910 ret i64 %old
911}
912
913define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]914; CHECK-LABEL: test_atomic_cmpxchg_i8:
Tim Northovere94a5182014-03-11 10:48:52 +0000[diff] [blame]915 %old = cmpxchg i8* @var8, i8 %wanted, i8 %new acquire acquire
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]916; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]917; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]918; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]919
920; CHECK: [[STARTAGAIN:.LBB[0-9]+_[0-9]+]]:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]921; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]922 ; w0 below is a reasonable guess but could change: it certainly comes into the
923 ; function there.
924; CHECK-NEXT: cmp w[[OLD]], w0
925; CHECK-NEXT: b.ne [[GET_OUT:.LBB[0-9]+_[0-9]+]]
926 ; As above, w1 is a reasonable guess.
927; CHECK: stxrb [[STATUS:w[0-9]+]], w1, [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]928; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]]
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]929; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]930
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]931; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]932 ret i8 %old
933}
934
935define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]936; CHECK-LABEL: test_atomic_cmpxchg_i16:
Tim Northovere94a5182014-03-11 10:48:52 +0000[diff] [blame]937 %old = cmpxchg i16* @var16, i16 %wanted, i16 %new seq_cst seq_cst
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]938; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]939; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]940; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]941
942; CHECK: [[STARTAGAIN:.LBB[0-9]+_[0-9]+]]:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]943; CHECK: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]944 ; w0 below is a reasonable guess but could change: it certainly comes into the
945 ; function there.
946; CHECK-NEXT: cmp w[[OLD]], w0
947; CHECK-NEXT: b.ne [[GET_OUT:.LBB[0-9]+_[0-9]+]]
948 ; As above, w1 is a reasonable guess.
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]949; CHECK: stlxrh [[STATUS:w[0-9]+]], w1, [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]950; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]]
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]951; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]952
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]953; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]954 ret i16 %old
955}
956
957define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]958; CHECK-LABEL: test_atomic_cmpxchg_i32:
Tim Northovere94a5182014-03-11 10:48:52 +0000[diff] [blame]959 %old = cmpxchg i32* @var32, i32 %wanted, i32 %new release monotonic
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]960; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]961; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]962; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]963
964; CHECK: [[STARTAGAIN:.LBB[0-9]+_[0-9]+]]:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]965; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]966 ; w0 below is a reasonable guess but could change: it certainly comes into the
967 ; function there.
968; CHECK-NEXT: cmp w[[OLD]], w0
969; CHECK-NEXT: b.ne [[GET_OUT:.LBB[0-9]+_[0-9]+]]
970 ; As above, w1 is a reasonable guess.
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]971; CHECK: stlxr [[STATUS:w[0-9]+]], w1, [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]972; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]]
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]973; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]974
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]975; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]976 ret i32 %old
977}
978
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]979define void @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]980; CHECK-LABEL: test_atomic_cmpxchg_i64:
Tim Northovere94a5182014-03-11 10:48:52 +0000[diff] [blame]981 %old = cmpxchg i64* @var64, i64 %wanted, i64 %new monotonic monotonic
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]982; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]983; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]984; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]985
986; CHECK: [[STARTAGAIN:.LBB[0-9]+_[0-9]+]]:
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]987; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]988 ; w0 below is a reasonable guess but could change: it certainly comes into the
989 ; function there.
990; CHECK-NEXT: cmp x[[OLD]], x0
991; CHECK-NEXT: b.ne [[GET_OUT:.LBB[0-9]+_[0-9]+]]
992 ; As above, w1 is a reasonable guess.
993; CHECK: stxr [[STATUS:w[0-9]+]], x1, [x[[ADDR]]]
Tim Northover9fafdf62013-02-28 13:52:07 +0000[diff] [blame]994; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]]
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]995; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]996
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]997; CHECK: str x[[OLD]],
998 store i64 %old, i64* @var64
999 ret void
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1000}
1001
1002define i8 @test_atomic_load_monotonic_i8() nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]1003; CHECK-LABEL: test_atomic_load_monotonic_i8:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1004 %val = load atomic i8* @var8 monotonic, align 1
1005; CHECK-NOT: dmb
1006; CHECK: adrp x[[HIADDR:[0-9]+]], var8
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]1007; CHECK: ldrb w0, [x[[HIADDR]], {{#?}}:lo12:var8]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1008; CHECK-NOT: dmb
1009
1010 ret i8 %val
1011}
1012
1013define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]1014; CHECK-LABEL: test_atomic_load_monotonic_regoff_i8:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1015 %addr_int = add i64 %base, %off
1016 %addr = inttoptr i64 %addr_int to i8*
1017
1018 %val = load atomic i8* %addr monotonic, align 1
1019; CHECK-NOT: dmb
1020; CHECK: ldrb w0, [x0, x1]
1021; CHECK-NOT: dmb
1022
1023 ret i8 %val
1024}
1025
1026define i8 @test_atomic_load_acquire_i8() nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]1027; CHECK-LABEL: test_atomic_load_acquire_i8:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1028 %val = load atomic i8* @var8 acquire, align 1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1029; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1030; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1031; CHECK-NOT: dmb
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]1032; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1033; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1034; CHECK: ldarb w0, [x[[ADDR]]]
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1035; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1036 ret i8 %val
1037}
1038
1039define i8 @test_atomic_load_seq_cst_i8() nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]1040; CHECK-LABEL: test_atomic_load_seq_cst_i8:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1041 %val = load atomic i8* @var8 seq_cst, align 1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1042; CHECK-NOT: dmb
1043; CHECK: adrp [[HIADDR:x[0-9]+]], var8
1044; CHECK-NOT: dmb
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]1045; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], {{#?}}:lo12:var8
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1046; CHECK-NOT: dmb
1047; CHECK: ldarb w0, [x[[ADDR]]]
1048; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1049 ret i8 %val
1050}
1051
1052define i16 @test_atomic_load_monotonic_i16() nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]1053; CHECK-LABEL: test_atomic_load_monotonic_i16:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1054 %val = load atomic i16* @var16 monotonic, align 2
1055; CHECK-NOT: dmb
1056; CHECK: adrp x[[HIADDR:[0-9]+]], var16
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1057; CHECK-NOT: dmb
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]1058; CHECK: ldrh w0, [x[[HIADDR]], {{#?}}:lo12:var16]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1059; CHECK-NOT: dmb
1060
1061 ret i16 %val
1062}
1063
1064define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]1065; CHECK-LABEL: test_atomic_load_monotonic_regoff_i32:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1066 %addr_int = add i64 %base, %off
1067 %addr = inttoptr i64 %addr_int to i32*
1068
1069 %val = load atomic i32* %addr monotonic, align 4
1070; CHECK-NOT: dmb
1071; CHECK: ldr w0, [x0, x1]
1072; CHECK-NOT: dmb
1073
1074 ret i32 %val
1075}
1076
1077define i64 @test_atomic_load_seq_cst_i64() nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]1078; CHECK-LABEL: test_atomic_load_seq_cst_i64:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1079 %val = load atomic i64* @var64 seq_cst, align 8
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1080; CHECK-NOT: dmb
1081; CHECK: adrp [[HIADDR:x[0-9]+]], var64
1082; CHECK-NOT: dmb
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]1083; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], {{#?}}:lo12:var64
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1084; CHECK-NOT: dmb
1085; CHECK: ldar x0, [x[[ADDR]]]
1086; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1087 ret i64 %val
1088}
1089
1090define void @test_atomic_store_monotonic_i8(i8 %val) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]1091; CHECK-LABEL: test_atomic_store_monotonic_i8:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1092 store atomic i8 %val, i8* @var8 monotonic, align 1
1093; CHECK: adrp x[[HIADDR:[0-9]+]], var8
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]1094; CHECK: strb w0, [x[[HIADDR]], {{#?}}:lo12:var8]
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1095
1096 ret void
1097}
1098
1099define void @test_atomic_store_monotonic_regoff_i8(i64 %base, i64 %off, i8 %val) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]1100; CHECK-LABEL: test_atomic_store_monotonic_regoff_i8:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1101
1102 %addr_int = add i64 %base, %off
1103 %addr = inttoptr i64 %addr_int to i8*
1104
1105 store atomic i8 %val, i8* %addr monotonic, align 1
1106; CHECK: strb w2, [x0, x1]
1107
1108 ret void
1109}
1110define void @test_atomic_store_release_i8(i8 %val) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]1111; CHECK-LABEL: test_atomic_store_release_i8:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1112 store atomic i8 %val, i8* @var8 release, align 1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1113; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1114; CHECK: adrp [[HIADDR:x[0-9]+]], var8
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1115; CHECK-NOT: dmb
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]1116; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], {{#?}}:lo12:var8
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1117; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1118; CHECK: stlrb w0, [x[[ADDR]]]
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1119; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1120 ret void
1121}
1122
1123define void @test_atomic_store_seq_cst_i8(i8 %val) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]1124; CHECK-LABEL: test_atomic_store_seq_cst_i8:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1125 store atomic i8 %val, i8* @var8 seq_cst, align 1
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1126; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1127; CHECK: adrp [[HIADDR:x[0-9]+]], var8
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1128; CHECK-NOT: dmb
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]1129; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], {{#?}}:lo12:var8
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1130; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1131; CHECK: stlrb w0, [x[[ADDR]]]
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1132; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1133
1134 ret void
1135}
1136
1137define void @test_atomic_store_monotonic_i16(i16 %val) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]1138; CHECK-LABEL: test_atomic_store_monotonic_i16:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1139 store atomic i16 %val, i16* @var16 monotonic, align 2
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1140; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1141; CHECK: adrp x[[HIADDR:[0-9]+]], var16
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1142; CHECK-NOT: dmb
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]1143; CHECK: strh w0, [x[[HIADDR]], {{#?}}:lo12:var16]
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1144; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1145 ret void
1146}
1147
1148define void @test_atomic_store_monotonic_regoff_i32(i64 %base, i64 %off, i32 %val) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]1149; CHECK-LABEL: test_atomic_store_monotonic_regoff_i32:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1150
1151 %addr_int = add i64 %base, %off
1152 %addr = inttoptr i64 %addr_int to i32*
1153
1154 store atomic i32 %val, i32* %addr monotonic, align 4
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1155; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1156; CHECK: str w2, [x0, x1]
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1157; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1158
1159 ret void
1160}
1161
1162define void @test_atomic_store_release_i64(i64 %val) nounwind {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]1163; CHECK-LABEL: test_atomic_store_release_i64:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1164 store atomic i64 %val, i64* @var64 release, align 8
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1165; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1166; CHECK: adrp [[HIADDR:x[0-9]+]], var64
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1167; CHECK-NOT: dmb
Tim Northover66c36b82014-04-18 09:31:31 +0000[diff] [blame^]1168; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], {{#?}}:lo12:var64
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1169; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1170; CHECK: stlr x0, [x[[ADDR]]]
Tim Northover15410e92013-04-08 08:40:41 +0000[diff] [blame]1171; CHECK-NOT: dmb
Tim Northovere0e3aef2013-01-31 12:12:40 +0000[diff] [blame]1172 ret void
1173}