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Eugene Zelenkofa912a72017-02-27 22:45:06 +00001//===- llvm/Target/TargetSchedule.cpp - Sched Machine Model ---------------===//
Andrew Trickd2a19da2012-09-14 20:26:46 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements a wrapper around MCSchedModel that allows the interface
11// to benefit from information currently only available in TargetInstrInfo.
12//
13//===----------------------------------------------------------------------===//
14
Chandler Carruth6bda14b2017-06-06 11:49:48 +000015#include "llvm/CodeGen/TargetSchedule.h"
Eugene Zelenkofa912a72017-02-27 22:45:06 +000016#include "llvm/CodeGen/MachineFunction.h"
17#include "llvm/CodeGen/MachineInstr.h"
18#include "llvm/CodeGen/MachineOperand.h"
Eugene Zelenkofa912a72017-02-27 22:45:06 +000019#include "llvm/MC/MCInstrDesc.h"
20#include "llvm/MC/MCInstrItineraries.h"
21#include "llvm/MC/MCSchedule.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000022#include "llvm/Support/CommandLine.h"
Eugene Zelenkofa912a72017-02-27 22:45:06 +000023#include "llvm/Support/ErrorHandling.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000024#include "llvm/Support/raw_ostream.h"
Andrew Trickd2a19da2012-09-14 20:26:46 +000025#include "llvm/Target/TargetInstrInfo.h"
Andrew Trick6e6d5972012-09-18 04:03:34 +000026#include "llvm/Target/TargetRegisterInfo.h"
Andrew Trickd2a19da2012-09-14 20:26:46 +000027#include "llvm/Target/TargetSubtargetInfo.h"
Eugene Zelenkofa912a72017-02-27 22:45:06 +000028#include <algorithm>
29#include <cassert>
30#include <cstdint>
Andrew Trickd2a19da2012-09-14 20:26:46 +000031
32using namespace llvm;
33
Andrew Trick8abcf4d2012-10-04 00:24:34 +000034static cl::opt<bool> EnableSchedModel("schedmodel", cl::Hidden, cl::init(true),
Andrew Trickd2a19da2012-09-14 20:26:46 +000035 cl::desc("Use TargetSchedModel for latency lookup"));
36
Andrew Trick6e6d5972012-09-18 04:03:34 +000037static cl::opt<bool> EnableSchedItins("scheditins", cl::Hidden, cl::init(true),
38 cl::desc("Use InstrItineraryData for latency lookup"));
39
Andrew Trickcfcf5202012-10-09 23:44:26 +000040bool TargetSchedModel::hasInstrSchedModel() const {
41 return EnableSchedModel && SchedModel.hasInstrSchedModel();
42}
43
44bool TargetSchedModel::hasInstrItineraries() const {
45 return EnableSchedItins && !InstrItins.isEmpty();
46}
47
Andrew Tricke96390e2012-11-06 07:10:38 +000048static unsigned gcd(unsigned Dividend, unsigned Divisor) {
49 // Dividend and Divisor will be naturally swapped as needed.
Eugene Zelenkofa912a72017-02-27 22:45:06 +000050 while (Divisor) {
Andrew Tricke96390e2012-11-06 07:10:38 +000051 unsigned Rem = Dividend % Divisor;
52 Dividend = Divisor;
53 Divisor = Rem;
54 };
55 return Dividend;
56}
Eugene Zelenkofa912a72017-02-27 22:45:06 +000057
Andrew Tricke96390e2012-11-06 07:10:38 +000058static unsigned lcm(unsigned A, unsigned B) {
59 unsigned LCM = (uint64_t(A) * B) / gcd(A, B);
60 assert((LCM >= A && LCM >= B) && "LCM overflow");
61 return LCM;
62}
63
Andrew Trickd2a19da2012-09-14 20:26:46 +000064void TargetSchedModel::init(const MCSchedModel &sm,
65 const TargetSubtargetInfo *sti,
66 const TargetInstrInfo *tii) {
67 SchedModel = sm;
68 STI = sti;
69 TII = tii;
70 STI->initInstrItins(InstrItins);
Andrew Tricke96390e2012-11-06 07:10:38 +000071
72 unsigned NumRes = SchedModel.getNumProcResourceKinds();
73 ResourceFactors.resize(NumRes);
74 ResourceLCM = SchedModel.IssueWidth;
75 for (unsigned Idx = 0; Idx < NumRes; ++Idx) {
76 unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
77 if (NumUnits > 0)
78 ResourceLCM = lcm(ResourceLCM, NumUnits);
79 }
80 MicroOpFactor = ResourceLCM / SchedModel.IssueWidth;
81 for (unsigned Idx = 0; Idx < NumRes; ++Idx) {
82 unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
83 ResourceFactors[Idx] = NumUnits ? (ResourceLCM / NumUnits) : 0;
84 }
Andrew Trickd2a19da2012-09-14 20:26:46 +000085}
Andrew Trick6e6d5972012-09-18 04:03:34 +000086
Javed Absar3d594372017-03-27 20:46:37 +000087/// Returns true only if instruction is specified as single issue.
88bool TargetSchedModel::mustBeginGroup(const MachineInstr *MI,
89 const MCSchedClassDesc *SC) const {
90 if (hasInstrSchedModel()) {
91 if (!SC)
92 SC = resolveSchedClass(MI);
93 if (SC->isValid())
94 return SC->BeginGroup;
95 }
96 return false;
97}
98
99bool TargetSchedModel::mustEndGroup(const MachineInstr *MI,
100 const MCSchedClassDesc *SC) const {
101 if (hasInstrSchedModel()) {
102 if (!SC)
103 SC = resolveSchedClass(MI);
104 if (SC->isValid())
105 return SC->EndGroup;
106 }
107 return false;
108}
109
Andrew Tricke96390e2012-11-06 07:10:38 +0000110unsigned TargetSchedModel::getNumMicroOps(const MachineInstr *MI,
111 const MCSchedClassDesc *SC) const {
Andrew Trickdd79f0f2012-10-10 05:43:09 +0000112 if (hasInstrItineraries()) {
113 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass());
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000114 return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, *MI);
Andrew Trickdd79f0f2012-10-10 05:43:09 +0000115 }
Andrew Trick5f35afb2012-10-11 05:37:06 +0000116 if (hasInstrSchedModel()) {
Andrew Tricke96390e2012-11-06 07:10:38 +0000117 if (!SC)
118 SC = resolveSchedClass(MI);
119 if (SC->isValid())
120 return SC->NumMicroOps;
Andrew Trick5f35afb2012-10-11 05:37:06 +0000121 }
122 return MI->isTransient() ? 0 : 1;
Andrew Trickdd79f0f2012-10-10 05:43:09 +0000123}
124
Andrew Trick0b1d8d02012-10-17 17:27:10 +0000125// The machine model may explicitly specify an invalid latency, which
126// effectively means infinite latency. Since users of the TargetSchedule API
127// don't know how to handle this, we convert it to a very large latency that is
128// easy to distinguish when debugging the DAG but won't induce overflow.
Andrew Trickde2109e2013-06-15 04:49:57 +0000129static unsigned capLatency(int Cycles) {
Andrew Trick0b1d8d02012-10-17 17:27:10 +0000130 return Cycles >= 0 ? Cycles : 1000;
131}
132
Andrew Trick6e6d5972012-09-18 04:03:34 +0000133/// Return the MCSchedClassDesc for this instruction. Some SchedClasses require
134/// evaluation of predicates that depend on instruction operands or flags.
135const MCSchedClassDesc *TargetSchedModel::
136resolveSchedClass(const MachineInstr *MI) const {
Andrew Trick6e6d5972012-09-18 04:03:34 +0000137 // Get the definition's scheduling class descriptor from this machine model.
138 unsigned SchedClass = MI->getDesc().getSchedClass();
139 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass);
Andrew Trickbe2bccb2013-04-13 06:07:45 +0000140 if (!SCDesc->isValid())
141 return SCDesc;
Andrew Trick6e6d5972012-09-18 04:03:34 +0000142
143#ifndef NDEBUG
144 unsigned NIter = 0;
145#endif
146 while (SCDesc->isVariant()) {
147 assert(++NIter < 6 && "Variants are nested deeper than the magic number");
148
149 SchedClass = STI->resolveSchedClass(SchedClass, MI, this);
150 SCDesc = SchedModel.getSchedClassDesc(SchedClass);
151 }
152 return SCDesc;
153}
154
155/// Find the def index of this operand. This index maps to the machine model and
156/// is independent of use operands. Def operands may be reordered with uses or
157/// merged with uses without affecting the def index (e.g. before/after
158/// regalloc). However, an instruction's def operands must never be reordered
159/// with respect to each other.
160static unsigned findDefIdx(const MachineInstr *MI, unsigned DefOperIdx) {
161 unsigned DefIdx = 0;
162 for (unsigned i = 0; i != DefOperIdx; ++i) {
163 const MachineOperand &MO = MI->getOperand(i);
164 if (MO.isReg() && MO.isDef())
165 ++DefIdx;
166 }
167 return DefIdx;
168}
169
170/// Find the use index of this operand. This is independent of the instruction's
171/// def operands.
Andrew Trickf2b70d92012-09-18 18:20:02 +0000172///
173/// Note that uses are not determined by the operand's isUse property, which
174/// is simply the inverse of isDef. Here we consider any readsReg operand to be
175/// a "use". The machine model allows an operand to be both a Def and Use.
Andrew Trick6e6d5972012-09-18 04:03:34 +0000176static unsigned findUseIdx(const MachineInstr *MI, unsigned UseOperIdx) {
177 unsigned UseIdx = 0;
178 for (unsigned i = 0; i != UseOperIdx; ++i) {
179 const MachineOperand &MO = MI->getOperand(i);
Matthias Braun3a133152016-08-24 02:32:29 +0000180 if (MO.isReg() && MO.readsReg() && !MO.isDef())
Andrew Trick6e6d5972012-09-18 04:03:34 +0000181 ++UseIdx;
182 }
183 return UseIdx;
184}
185
186// Top-level API for clients that know the operand indices.
187unsigned TargetSchedModel::computeOperandLatency(
188 const MachineInstr *DefMI, unsigned DefOperIdx,
Andrew Trickde2109e2013-06-15 04:49:57 +0000189 const MachineInstr *UseMI, unsigned UseOperIdx) const {
Andrew Trick6e6d5972012-09-18 04:03:34 +0000190
Andrew Trickde2109e2013-06-15 04:49:57 +0000191 if (!hasInstrSchedModel() && !hasInstrItineraries())
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000192 return TII->defaultDefLatency(SchedModel, *DefMI);
Andrew Trick6e6d5972012-09-18 04:03:34 +0000193
Andrew Trickcfcf5202012-10-09 23:44:26 +0000194 if (hasInstrItineraries()) {
Andrew Trick8abcf4d2012-10-04 00:24:34 +0000195 int OperLatency = 0;
196 if (UseMI) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000197 OperLatency = TII->getOperandLatency(&InstrItins, *DefMI, DefOperIdx,
198 *UseMI, UseOperIdx);
Andrew Trick6e6d5972012-09-18 04:03:34 +0000199 }
Andrew Trick8abcf4d2012-10-04 00:24:34 +0000200 else {
201 unsigned DefClass = DefMI->getDesc().getSchedClass();
202 OperLatency = InstrItins.getOperandCycle(DefClass, DefOperIdx);
203 }
204 if (OperLatency >= 0)
205 return OperLatency;
206
207 // No operand latency was found.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000208 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, *DefMI);
Andrew Trick8abcf4d2012-10-04 00:24:34 +0000209
210 // Expected latency is the max of the stage latency and itinerary props.
Andrew Trick780fae82012-10-09 23:44:32 +0000211 // Rather than directly querying InstrItins stage latency, we call a TII
212 // hook to allow subtargets to specialize latency. This hook is only
213 // applicable to the InstrItins model. InstrSchedModel should model all
214 // special cases without TII hooks.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000215 InstrLatency =
216 std::max(InstrLatency, TII->defaultDefLatency(SchedModel, *DefMI));
Andrew Trick8abcf4d2012-10-04 00:24:34 +0000217 return InstrLatency;
218 }
Andrew Trickde2109e2013-06-15 04:49:57 +0000219 // hasInstrSchedModel()
Andrew Trick8abcf4d2012-10-04 00:24:34 +0000220 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
221 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
222 if (DefIdx < SCDesc->NumWriteLatencyEntries) {
223 // Lookup the definition's write latency in SubtargetInfo.
224 const MCWriteLatencyEntry *WLEntry =
225 STI->getWriteLatencyEntry(SCDesc, DefIdx);
226 unsigned WriteID = WLEntry->WriteResourceID;
Andrew Trickde2109e2013-06-15 04:49:57 +0000227 unsigned Latency = capLatency(WLEntry->Cycles);
Andrew Trick8abcf4d2012-10-04 00:24:34 +0000228 if (!UseMI)
229 return Latency;
230
231 // Lookup the use's latency adjustment in SubtargetInfo.
232 const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI);
233 if (UseDesc->NumReadAdvanceEntries == 0)
234 return Latency;
235 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx);
Andrew Trick5d4861862013-06-17 21:45:18 +0000236 int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
237 if (Advance > 0 && (unsigned)Advance > Latency) // unsigned wrap
238 return 0;
239 return Latency - Advance;
Andrew Trick8abcf4d2012-10-04 00:24:34 +0000240 }
241 // If DefIdx does not exist in the model (e.g. implicit defs), then return
242 // unit latency (defaultDefLatency may be too conservative).
Andrew Trickf2b70d92012-09-18 18:20:02 +0000243#ifndef NDEBUG
Andrew Trick8abcf4d2012-10-04 00:24:34 +0000244 if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit()
Andrew Trickb6854d82013-09-25 18:14:12 +0000245 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()
246 && SchedModel.isComplete()) {
Matthias Braun244a6772015-07-17 17:50:11 +0000247 errs() << "DefIdx " << DefIdx << " exceeds machine model writes for "
MinSeong Kim4a9a4e12016-01-05 14:50:15 +0000248 << *DefMI << " (Try with MCSchedModel.CompleteModel set to false)";
Matthias Braun244a6772015-07-17 17:50:11 +0000249 llvm_unreachable("incomplete machine model");
Andrew Trick8abcf4d2012-10-04 00:24:34 +0000250 }
Andrew Trickf2b70d92012-09-18 18:20:02 +0000251#endif
Andrew Trick60570172013-03-16 18:58:57 +0000252 // FIXME: Automatically giving all implicit defs defaultDefLatency is
253 // undesirable. We should only do it for defs that are known to the MC
254 // desc like flags. Truly implicit defs should get 1 cycle latency.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000255 return DefMI->isTransient() ? 0 : TII->defaultDefLatency(SchedModel, *DefMI);
Andrew Trick6e6d5972012-09-18 04:03:34 +0000256}
Andrew Trick780fae82012-10-09 23:44:32 +0000257
Matthias Braun42e1e662015-05-14 18:01:13 +0000258unsigned
259TargetSchedModel::computeInstrLatency(const MCSchedClassDesc &SCDesc) const {
260 unsigned Latency = 0;
261 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries;
262 DefIdx != DefEnd; ++DefIdx) {
263 // Lookup the definition's write latency in SubtargetInfo.
264 const MCWriteLatencyEntry *WLEntry =
265 STI->getWriteLatencyEntry(&SCDesc, DefIdx);
266 Latency = std::max(Latency, capLatency(WLEntry->Cycles));
267 }
268 return Latency;
269}
270
Gerolf Hoflehner5e1207e2014-08-03 21:35:39 +0000271unsigned TargetSchedModel::computeInstrLatency(unsigned Opcode) const {
272 assert(hasInstrSchedModel() && "Only call this function with a SchedModel");
273
274 unsigned SCIdx = TII->get(Opcode).getSchedClass();
275 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SCIdx);
Gerolf Hoflehner5e1207e2014-08-03 21:35:39 +0000276
Matthias Braun42e1e662015-05-14 18:01:13 +0000277 if (SCDesc->isValid() && !SCDesc->isVariant())
278 return computeInstrLatency(*SCDesc);
Gerolf Hoflehner5e1207e2014-08-03 21:35:39 +0000279
Andrew V. Tischenko75745d02017-04-14 07:44:23 +0000280 if (SCDesc->isValid()) {
281 assert (!SCDesc->isVariant() && "No MI sched latency: SCDesc->isVariant()");
282 return computeInstrLatency(*SCDesc);
283 }
284 return 0;
Gerolf Hoflehner5e1207e2014-08-03 21:35:39 +0000285}
286
Arnold Schwaighoferd2f96b92013-09-30 15:28:56 +0000287unsigned
288TargetSchedModel::computeInstrLatency(const MachineInstr *MI,
289 bool UseDefaultDefLatency) const {
Andrew Trickc334bd42012-10-10 05:43:18 +0000290 // For the itinerary model, fall back to the old subtarget hook.
291 // Allow subtargets to compute Bundle latencies outside the machine model.
Arnold Schwaighoferd2f96b92013-09-30 15:28:56 +0000292 if (hasInstrItineraries() || MI->isBundle() ||
293 (!hasInstrSchedModel() && !UseDefaultDefLatency))
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000294 return TII->getInstrLatency(&InstrItins, *MI);
Andrew Trickc334bd42012-10-10 05:43:18 +0000295
Andrew Trick780fae82012-10-09 23:44:32 +0000296 if (hasInstrSchedModel()) {
Andrew Trick780fae82012-10-09 23:44:32 +0000297 const MCSchedClassDesc *SCDesc = resolveSchedClass(MI);
Matthias Braun42e1e662015-05-14 18:01:13 +0000298 if (SCDesc->isValid())
299 return computeInstrLatency(*SCDesc);
Andrew Trick780fae82012-10-09 23:44:32 +0000300 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000301 return TII->defaultDefLatency(SchedModel, *MI);
Andrew Trick780fae82012-10-09 23:44:32 +0000302}
Andrew Trickdd79f0f2012-10-10 05:43:09 +0000303
304unsigned TargetSchedModel::
305computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
306 const MachineInstr *DepMI) const {
Junmo Park11811922016-06-21 08:09:58 +0000307 if (!SchedModel.isOutOfOrder())
Andrew Trickdd79f0f2012-10-10 05:43:09 +0000308 return 1;
309
Junmo Park11811922016-06-21 08:09:58 +0000310 // Out-of-order processor can dispatch WAW dependencies in the same cycle.
Andrew Trickdd79f0f2012-10-10 05:43:09 +0000311
312 // Treat predication as a data dependency for out-of-order cpus. In-order
313 // cpus do not need to treat predicated writes specially.
314 //
315 // TODO: The following hack exists because predication passes do not
316 // correctly append imp-use operands, and readsReg() strangely returns false
317 // for predicated defs.
318 unsigned Reg = DefMI->getOperand(DefOperIdx).getReg();
319 const MachineFunction &MF = *DefMI->getParent()->getParent();
Eric Christopherfc6de422014-08-05 02:39:49 +0000320 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000321 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(*DepMI))
Andrew Trickdd79f0f2012-10-10 05:43:09 +0000322 return computeInstrLatency(DefMI);
323
324 // If we have a per operand scheduling model, check if this def is writing
325 // an unbuffered resource. If so, it treated like an in-order cpu.
326 if (hasInstrSchedModel()) {
327 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
Andrew Trick5f35afb2012-10-11 05:37:06 +0000328 if (SCDesc->isValid()) {
329 for (const MCWriteProcResEntry *PRI = STI->getWriteProcResBegin(SCDesc),
330 *PRE = STI->getWriteProcResEnd(SCDesc); PRI != PRE; ++PRI) {
Andrew Trickde2109e2013-06-15 04:49:57 +0000331 if (!SchedModel.getProcResource(PRI->ProcResourceIdx)->BufferSize)
Andrew Trick5f35afb2012-10-11 05:37:06 +0000332 return 1;
333 }
Andrew Trickdd79f0f2012-10-10 05:43:09 +0000334 }
335 }
336 return 0;
337}
Andrew V. Tischenko75745d02017-04-14 07:44:23 +0000338
339static Optional<double>
340getRTroughputFromItineraries(unsigned schedClass,
341 const InstrItineraryData *IID){
342 double Unknown = std::numeric_limits<double>::infinity();
343 double Throughput = Unknown;
344
345 for (const InstrStage *IS = IID->beginStage(schedClass),
346 *E = IID->endStage(schedClass);
347 IS != E; ++IS) {
348 unsigned Cycles = IS->getCycles();
349 if (!Cycles)
350 continue;
351 Throughput =
352 std::min(Throughput, countPopulation(IS->getUnits()) * 1.0 / Cycles);
353 }
354 // We need reciprocal throughput that's why we return such value.
355 return 1 / Throughput;
356}
357
358static Optional<double>
359getRTroughputFromInstrSchedModel(const MCSchedClassDesc *SCDesc,
360 const TargetSubtargetInfo *STI,
361 const MCSchedModel &SchedModel) {
362 double Unknown = std::numeric_limits<double>::infinity();
363 double Throughput = Unknown;
364
365 for (const MCWriteProcResEntry *WPR = STI->getWriteProcResBegin(SCDesc),
366 *WEnd = STI->getWriteProcResEnd(SCDesc);
367 WPR != WEnd; ++WPR) {
368 unsigned Cycles = WPR->Cycles;
369 if (!Cycles)
370 return Optional<double>();
371
372 unsigned NumUnits =
373 SchedModel.getProcResource(WPR->ProcResourceIdx)->NumUnits;
374 Throughput = std::min(Throughput, NumUnits * 1.0 / Cycles);
375 }
376 // We need reciprocal throughput that's why we return such value.
377 return 1 / Throughput;
378}
379
380Optional<double>
381TargetSchedModel::computeInstrRThroughput(const MachineInstr *MI) const {
382 if (hasInstrItineraries())
383 return getRTroughputFromItineraries(MI->getDesc().getSchedClass(),
384 getInstrItineraries());
385 if (hasInstrSchedModel())
386 return getRTroughputFromInstrSchedModel(resolveSchedClass(MI), STI,
387 SchedModel);
388 return Optional<double>();
389}
390
391Optional<double>
392TargetSchedModel::computeInstrRThroughput(unsigned Opcode) const {
393 unsigned SchedClass = TII->get(Opcode).getSchedClass();
394 if (hasInstrItineraries())
395 return getRTroughputFromItineraries(SchedClass, getInstrItineraries());
396 if (hasInstrSchedModel()) {
397 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass);
398 if (SCDesc->isValid() && !SCDesc->isVariant())
399 return getRTroughputFromInstrSchedModel(SCDesc, STI, SchedModel);
400 }
401 return Optional<double>();
402}