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gerrit-public.fairphone.software / toolchain / llvm-project / 708a91a10366f0aa8f2b3912dd8e047ca1a66e5b / . / llvm / test / CodeGen / AMDGPU / sign_extend.ll
blob: 06bee114c23a450aeb8825dce4b72f66d1a48309 [file] [log] [blame]
Tom Stellard49f8bfd2015-01-06 18:00:21 +0000[diff] [blame]1; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
Marek Olsak75170772015-01-27 17:27:15 +0000[diff] [blame]2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
Tom Stellard046039e2013-06-03 17:40:03 +0000[diff] [blame]3
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame]4; SI-LABEL: {{^}}s_sext_i1_to_i32:
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]5; SI: v_cndmask_b32_e64
6; SI: s_endpgm
Matt Arsenaultb2cbf792014-06-10 18:54:59 +0000[diff] [blame]7define void @s_sext_i1_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
8 %cmp = icmp eq i32 %a, %b
9 %sext = sext i1 %cmp to i32
10 store i32 %sext, i32 addrspace(1)* %out, align 4
11 ret void
12}
Tom Stellard046039e2013-06-03 17:40:03 +0000[diff] [blame]13
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame]14; SI-LABEL: {{^}}test_s_sext_i32_to_i64:
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]15; SI: s_ashr_i32
16; SI: s_endpg
Matt Arsenault869cd072014-09-03 23:24:35 +0000[diff] [blame]17define void @test_s_sext_i32_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) nounwind {
Tom Stellard046039e2013-06-03 17:40:03 +0000[diff] [blame]18entry:
Matt Arsenaultb2cbf792014-06-10 18:54:59 +0000[diff] [blame]19 %mul = mul i32 %a, %b
20 %add = add i32 %mul, %c
21 %sext = sext i32 %add to i64
22 store i64 %sext, i64 addrspace(1)* %out, align 8
23 ret void
24}
25
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame]26; SI-LABEL: {{^}}s_sext_i1_to_i64:
Matt Arsenault8a9e4042015-02-13 19:04:56 +0000[diff] [blame]27; SI: v_cndmask_b32_e64 v[[LOREG:[0-9]+]], 0, -1, vcc
28; SI: v_mov_b32_e32 v[[HIREG:[0-9]+]], v[[LOREG]]
29; SI: buffer_store_dwordx2 v{{\[}}[[LOREG]]:[[HIREG]]{{\]}}
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]30; SI: s_endpgm
Matt Arsenaultb2cbf792014-06-10 18:54:59 +0000[diff] [blame]31define void @s_sext_i1_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
32 %cmp = icmp eq i32 %a, %b
33 %sext = sext i1 %cmp to i64
34 store i64 %sext, i64 addrspace(1)* %out, align 8
35 ret void
36}
37
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame]38; SI-LABEL: {{^}}s_sext_i32_to_i64:
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]39; SI: s_ashr_i32
40; SI: s_endpgm
Matt Arsenaultb2cbf792014-06-10 18:54:59 +0000[diff] [blame]41define void @s_sext_i32_to_i64(i64 addrspace(1)* %out, i32 %a) nounwind {
42 %sext = sext i32 %a to i64
43 store i64 %sext, i64 addrspace(1)* %out, align 8
44 ret void
45}
46
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame]47; SI-LABEL: {{^}}v_sext_i32_to_i64:
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]48; SI: v_ashr
49; SI: s_endpgm
Matt Arsenaultb2cbf792014-06-10 18:54:59 +0000[diff] [blame]50define void @v_sext_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]51 %val = load i32, i32 addrspace(1)* %in, align 4
Matt Arsenaultb2cbf792014-06-10 18:54:59 +0000[diff] [blame]52 %sext = sext i32 %val to i64
53 store i64 %sext, i64 addrspace(1)* %out, align 8
54 ret void
55}
56
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame]57; SI-LABEL: {{^}}s_sext_i16_to_i64:
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]58; SI: s_endpgm
Matt Arsenaultb2cbf792014-06-10 18:54:59 +0000[diff] [blame]59define void @s_sext_i16_to_i64(i64 addrspace(1)* %out, i16 %a) nounwind {
60 %sext = sext i16 %a to i64
61 store i64 %sext, i64 addrspace(1)* %out, align 8
Tom Stellard046039e2013-06-03 17:40:03 +0000[diff] [blame]62 ret void
63}