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gerrit-public.fairphone.software / toolchain / llvm-project / 71369b3a3988d6a1a78d70ec87687905545650d9 / . / llvm / test / CodeGen / AMDGPU / fmin3.ll
blob: 2d1facfc3a40bba03440a894b49146729e3b82bc [file] [log] [blame]
Tom Stellard49f8bfd2015-01-06 18:00:21 +0000[diff] [blame]1; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
Marek Olsak75170772015-01-27 17:27:15 +0000[diff] [blame]2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
3; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
Matt Arsenaultcc3c2b32014-11-14 20:08:52 +0000[diff] [blame]4
5declare float @llvm.minnum.f32(float, float) nounwind readnone
6
7; SI-LABEL: {{^}}test_fmin3_olt_0:
Matt Arsenaultcc3c2b32014-11-14 20:08:52 +0000[diff] [blame]8; SI: buffer_load_dword [[REGC:v[0-9]+]]
Tom Stellard83f0bce2015-01-29 16:55:25 +0000[diff] [blame]9; SI: buffer_load_dword [[REGB:v[0-9]+]]
10; SI: buffer_load_dword [[REGA:v[0-9]+]]
Matt Arsenaultcc3c2b32014-11-14 20:08:52 +0000[diff] [blame]11; SI: v_min3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
12; SI: buffer_store_dword [[RESULT]],
13; SI: s_endpgm
14define void @test_fmin3_olt_0(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) nounwind {
Changpeng Fang71369b32016-05-26 19:35:29 +0000[diff] [blame^]15 %a = load volatile float, float addrspace(1)* %aptr, align 4
16 %b = load volatile float, float addrspace(1)* %bptr, align 4
17 %c = load volatile float, float addrspace(1)* %cptr, align 4
Matt Arsenaultcc3c2b32014-11-14 20:08:52 +0000[diff] [blame]18 %f0 = call float @llvm.minnum.f32(float %a, float %b) nounwind readnone
19 %f1 = call float @llvm.minnum.f32(float %f0, float %c) nounwind readnone
20 store float %f1, float addrspace(1)* %out, align 4
21 ret void
22}
23
24; Commute operand of second fmin
25; SI-LABEL: {{^}}test_fmin3_olt_1:
Matt Arsenaultcc3c2b32014-11-14 20:08:52 +0000[diff] [blame]26; SI: buffer_load_dword [[REGB:v[0-9]+]]
Tom Stellard83f0bce2015-01-29 16:55:25 +0000[diff] [blame]27; SI: buffer_load_dword [[REGA:v[0-9]+]]
Matt Arsenaultcc3c2b32014-11-14 20:08:52 +0000[diff] [blame]28; SI: buffer_load_dword [[REGC:v[0-9]+]]
29; SI: v_min3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
30; SI: buffer_store_dword [[RESULT]],
31; SI: s_endpgm
32define void @test_fmin3_olt_1(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) nounwind {
Changpeng Fang71369b32016-05-26 19:35:29 +0000[diff] [blame^]33 %a = load volatile float, float addrspace(1)* %aptr, align 4
34 %b = load volatile float, float addrspace(1)* %bptr, align 4
35 %c = load volatile float, float addrspace(1)* %cptr, align 4
Matt Arsenaultcc3c2b32014-11-14 20:08:52 +0000[diff] [blame]36 %f0 = call float @llvm.minnum.f32(float %a, float %b) nounwind readnone
37 %f1 = call float @llvm.minnum.f32(float %c, float %f0) nounwind readnone
38 store float %f1, float addrspace(1)* %out, align 4
39 ret void
40}