NAKAMURA Takumi | 729be14 | 2014-10-27 12:37:26 +0000 | [diff] [blame^] | 1 | //===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | |
| 10 | #include "MCTargetDesc/HexagonBaseInfo.h" |
| 11 | #include "MCTargetDesc/HexagonMCTargetDesc.h" |
| 12 | |
| 13 | #include "llvm/MC/MCContext.h" |
| 14 | #include "llvm/MC/MCDisassembler.h" |
| 15 | #include "llvm/MC/MCExpr.h" |
| 16 | #include "llvm/MC/MCFixedLenDisassembler.h" |
| 17 | #include "llvm/MC/MCInst.h" |
| 18 | #include "llvm/MC/MCInstrDesc.h" |
| 19 | #include "llvm/MC/MCSubtargetInfo.h" |
| 20 | #include "llvm/Support/Debug.h" |
| 21 | #include "llvm/Support/ErrorHandling.h" |
| 22 | #include "llvm/Support/LEB128.h" |
| 23 | #include "llvm/Support/MemoryObject.h" |
| 24 | #include "llvm/Support/raw_ostream.h" |
| 25 | #include "llvm/Support/TargetRegistry.h" |
| 26 | #include "llvm/Support/Endian.h" |
| 27 | |
| 28 | #include <vector> |
| 29 | #include <array> |
| 30 | |
| 31 | using namespace llvm; |
| 32 | |
| 33 | #define DEBUG_TYPE "hexagon-disassembler" |
| 34 | |
| 35 | // Pull DecodeStatus and its enum values into the global namespace. |
| 36 | typedef llvm::MCDisassembler::DecodeStatus DecodeStatus; |
| 37 | |
| 38 | namespace { |
| 39 | /// \brief Hexagon disassembler for all Hexagon platforms. |
| 40 | class HexagonDisassembler : public MCDisassembler { |
| 41 | public: |
| 42 | HexagonDisassembler(MCSubtargetInfo const &STI, MCContext &Ctx) |
| 43 | : MCDisassembler(STI, Ctx) {} |
| 44 | |
| 45 | DecodeStatus getInstruction(MCInst &instr, uint64_t &size, |
| 46 | MemoryObject const ®ion, uint64_t address, |
| 47 | raw_ostream &vStream, raw_ostream &cStream) const override; |
| 48 | }; |
| 49 | } |
| 50 | |
| 51 | static const uint16_t IntRegDecoderTable[] = { |
| 52 | Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, |
| 53 | Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, |
| 54 | Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14, |
| 55 | Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, |
| 56 | Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, |
| 57 | Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29, |
| 58 | Hexagon::R30, Hexagon::R31}; |
| 59 | |
| 60 | static const uint16_t PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1, |
| 61 | Hexagon::P2, Hexagon::P3}; |
| 62 | |
| 63 | static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, |
| 64 | uint64_t /*Address*/, |
| 65 | void const *Decoder) { |
| 66 | if (RegNo > 31) |
| 67 | return MCDisassembler::Fail; |
| 68 | |
| 69 | unsigned Register = IntRegDecoderTable[RegNo]; |
| 70 | Inst.addOperand(MCOperand::CreateReg(Register)); |
| 71 | return MCDisassembler::Success; |
| 72 | } |
| 73 | |
| 74 | static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, |
| 75 | uint64_t /*Address*/, |
| 76 | void const *Decoder) { |
| 77 | if (RegNo > 3) |
| 78 | return MCDisassembler::Fail; |
| 79 | |
| 80 | unsigned Register = PredRegDecoderTable[RegNo]; |
| 81 | Inst.addOperand(MCOperand::CreateReg(Register)); |
| 82 | return MCDisassembler::Success; |
| 83 | } |
| 84 | |
| 85 | #include "HexagonGenDisassemblerTables.inc" |
| 86 | |
| 87 | static MCDisassembler *createHexagonDisassembler(Target const &T, |
| 88 | MCSubtargetInfo const &STI, |
| 89 | MCContext &Ctx) { |
| 90 | return new HexagonDisassembler(STI, Ctx); |
| 91 | } |
| 92 | |
| 93 | extern "C" void LLVMInitializeHexagonDisassembler() { |
| 94 | TargetRegistry::RegisterMCDisassembler(TheHexagonTarget, |
| 95 | createHexagonDisassembler); |
| 96 | } |
| 97 | |
| 98 | DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, |
| 99 | MemoryObject const &Region, |
| 100 | uint64_t Address, |
| 101 | raw_ostream &os, |
| 102 | raw_ostream &cs) const { |
| 103 | std::array<uint8_t, 4> Bytes; |
| 104 | Size = 4; |
| 105 | if (Region.readBytes(Address, Bytes.size(), Bytes.data()) == -1) { |
| 106 | return MCDisassembler::Fail; |
| 107 | } |
| 108 | uint32_t insn = |
| 109 | llvm::support::endian::read<uint32_t, llvm::support::little, |
| 110 | llvm::support::unaligned>(Bytes.data()); |
| 111 | |
| 112 | // Remove parse bits. |
| 113 | insn &= ~static_cast<uint32_t>(HexagonII::InstParseBits::INST_PARSE_MASK); |
| 114 | return decodeInstruction(DecoderTable32, MI, insn, Address, this, STI); |
| 115 | } |