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gerrit-public.fairphone.software / toolchain / llvm-project / 73156025e021f98786009a06c794f8b8f369b7a3 / . / llvm / lib / Target / PowerPC / Disassembler / PPCDisassembler.cpp
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Hal Finkel23453472013-12-19 16:13:01 +0000[diff] [blame]1//===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "PPC.h"
11#include "llvm/MC/MCDisassembler.h"
12#include "llvm/MC/MCFixedLenDisassembler.h"
13#include "llvm/MC/MCInst.h"
14#include "llvm/MC/MCSubtargetInfo.h"
15#include "llvm/Support/MemoryObject.h"
16#include "llvm/Support/TargetRegistry.h"
17
18using namespace llvm;
19
20typedef MCDisassembler::DecodeStatus DecodeStatus;
21
22namespace {
23class PPCDisassembler : public MCDisassembler {
24public:
25 PPCDisassembler(const MCSubtargetInfo &STI)
26 : MCDisassembler(STI) {}
27 virtual ~PPCDisassembler() {}
28
29 // Override MCDisassembler.
30 virtual DecodeStatus getInstruction(MCInst &instr,
31 uint64_t &size,
32 const MemoryObject &region,
33 uint64_t address,
34 raw_ostream &vStream,
Craig Topper73156022014-03-02 09:09:27 +0000[diff] [blame^]35 raw_ostream &cStream) const override;
Hal Finkel23453472013-12-19 16:13:01 +0000[diff] [blame]36};
37} // end anonymous namespace
38
39static MCDisassembler *createPPCDisassembler(const Target &T,
40 const MCSubtargetInfo &STI) {
41 return new PPCDisassembler(STI);
42}
43
44extern "C" void LLVMInitializePowerPCDisassembler() {
45 // Register the disassembler for each target.
46 TargetRegistry::RegisterMCDisassembler(ThePPC32Target,
47 createPPCDisassembler);
48 TargetRegistry::RegisterMCDisassembler(ThePPC64Target,
49 createPPCDisassembler);
50 TargetRegistry::RegisterMCDisassembler(ThePPC64LETarget,
51 createPPCDisassembler);
52}
53
54// FIXME: These can be generated by TableGen from the existing register
55// encoding values!
56
57static const unsigned CRRegs[] = {
58 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
59 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
60};
61
62static const unsigned CRBITRegs[] = {
63 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
64 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
65 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
66 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
67 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
68 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
69 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
70 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
71};
72
73static const unsigned FRegs[] = {
74 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
75 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
76 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
77 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
78 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
79 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
80 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
81 PPC::F28, PPC::F29, PPC::F30, PPC::F31
82};
83
84static const unsigned VRegs[] = {
85 PPC::V0, PPC::V1, PPC::V2, PPC::V3,
86 PPC::V4, PPC::V5, PPC::V6, PPC::V7,
87 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
88 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
89 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
90 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
91 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
92 PPC::V28, PPC::V29, PPC::V30, PPC::V31
93};
94
95static const unsigned GPRegs[] = {
96 PPC::R0, PPC::R1, PPC::R2, PPC::R3,
97 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
98 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
99 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
100 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
101 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
102 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
103 PPC::R28, PPC::R29, PPC::R30, PPC::R31
104};
105
106static const unsigned GP0Regs[] = {
107 PPC::ZERO, PPC::R1, PPC::R2, PPC::R3,
108 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
109 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
110 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
111 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
112 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
113 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
114 PPC::R28, PPC::R29, PPC::R30, PPC::R31
115};
116
117static const unsigned G8Regs[] = {
118 PPC::X0, PPC::X1, PPC::X2, PPC::X3,
119 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
120 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
121 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
122 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
123 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
124 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
125 PPC::X28, PPC::X29, PPC::X30, PPC::X31
126};
127
128template <std::size_t N>
129static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
130 const unsigned (&Regs)[N]) {
131 assert(RegNo < N && "Invalid register number");
132 Inst.addOperand(MCOperand::CreateReg(Regs[RegNo]));
133 return MCDisassembler::Success;
134}
135
136static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
137 uint64_t Address,
138 const void *Decoder) {
139 return decodeRegisterClass(Inst, RegNo, CRRegs);
140}
141
142static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo,
143 uint64_t Address,
144 const void *Decoder) {
145 return decodeRegisterClass(Inst, RegNo, CRBITRegs);
146}
147
148static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo,
149 uint64_t Address,
150 const void *Decoder) {
151 return decodeRegisterClass(Inst, RegNo, FRegs);
152}
153
154static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
155 uint64_t Address,
156 const void *Decoder) {
157 return decodeRegisterClass(Inst, RegNo, FRegs);
158}
159
160static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
161 uint64_t Address,
162 const void *Decoder) {
163 return decodeRegisterClass(Inst, RegNo, VRegs);
164}
165
166static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
167 uint64_t Address,
168 const void *Decoder) {
169 return decodeRegisterClass(Inst, RegNo, GPRegs);
170}
171
172static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo,
173 uint64_t Address,
174 const void *Decoder) {
175 return decodeRegisterClass(Inst, RegNo, GP0Regs);
176}
177
178static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
179 uint64_t Address,
180 const void *Decoder) {
181 return decodeRegisterClass(Inst, RegNo, G8Regs);
182}
183
184#define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
185#define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
186
187template<unsigned N>
188static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
189 int64_t Address, const void *Decoder) {
190 assert(isUInt<N>(Imm) && "Invalid immediate");
191 Inst.addOperand(MCOperand::CreateImm(Imm));
192 return MCDisassembler::Success;
193}
194
195template<unsigned N>
196static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
197 int64_t Address, const void *Decoder) {
198 assert(isUInt<N>(Imm) && "Invalid immediate");
199 Inst.addOperand(MCOperand::CreateImm(SignExtend64<N>(Imm)));
200 return MCDisassembler::Success;
201}
202
203static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm,
204 int64_t Address, const void *Decoder) {
205 // Decode the memri field (imm, reg), which has the low 16-bits as the
206 // displacement and the next 5 bits as the register #.
207
208 uint64_t Base = Imm >> 16;
209 uint64_t Disp = Imm & 0xFFFF;
210
211 assert(Base < 32 && "Invalid base register");
212
213 switch (Inst.getOpcode()) {
214 default: break;
215 case PPC::LBZU:
216 case PPC::LHAU:
217 case PPC::LHZU:
218 case PPC::LWZU:
219 case PPC::LFSU:
220 case PPC::LFDU:
221 // Add the tied output operand.
222 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base]));
223 break;
224 case PPC::STBU:
225 case PPC::STHU:
226 case PPC::STWU:
227 case PPC::STFSU:
228 case PPC::STFDU:
229 Inst.insert(Inst.begin(), MCOperand::CreateReg(GP0Regs[Base]));
230 break;
231 }
232
233 Inst.addOperand(MCOperand::CreateImm(SignExtend64<16>(Disp)));
234 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base]));
235 return MCDisassembler::Success;
236}
237
238static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm,
239 int64_t Address, const void *Decoder) {
240 // Decode the memrix field (imm, reg), which has the low 14-bits as the
241 // displacement and the next 5 bits as the register #.
242
243 uint64_t Base = Imm >> 14;
244 uint64_t Disp = Imm & 0x3FFF;
245
246 assert(Base < 32 && "Invalid base register");
247
248 if (Inst.getOpcode() == PPC::LDU)
249 // Add the tied output operand.
250 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base]));
251 else if (Inst.getOpcode() == PPC::STDU)
252 Inst.insert(Inst.begin(), MCOperand::CreateReg(GP0Regs[Base]));
253
254 Inst.addOperand(MCOperand::CreateImm(SignExtend64<16>(Disp << 2)));
255 Inst.addOperand(MCOperand::CreateReg(GP0Regs[Base]));
256 return MCDisassembler::Success;
257}
258
259static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm,
260 int64_t Address, const void *Decoder) {
261 // The cr bit encoding is 0x80 >> cr_reg_num.
262
263 unsigned Zeros = countTrailingZeros(Imm);
264 assert(Zeros < 8 && "Invalid CR bit value");
265
266 Inst.addOperand(MCOperand::CreateReg(CRRegs[7 - Zeros]));
267 return MCDisassembler::Success;
268}
269
270#include "PPCGenDisassemblerTables.inc"
271
272DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
273 const MemoryObject &Region,
274 uint64_t Address,
275 raw_ostream &os,
276 raw_ostream &cs) const {
277 // Get the four bytes of the instruction.
278 uint8_t Bytes[4];
279 Size = 4;
280 if (Region.readBytes(Address, Size, Bytes) == -1) {
281 Size = 0;
282 return MCDisassembler::Fail;
283 }
284
285 // The instruction is big-endian encoded.
286 uint32_t Inst = (Bytes[0] << 24) |
287 (Bytes[1] << 16) |
288 (Bytes[2] << 8) |
289 (Bytes[3] << 0);
290
291 return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI);
292}
293