blob: 814ed59340a810797a5a2b01c8dada034ddcffc9 [file] [log] [blame]
Matt Arsenault2b252ec2014-07-28 18:06:08 +00001; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
2; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
Tom Stellard75aadc22012-12-11 21:25:42 +00003
Matt Arsenault2b252ec2014-07-28 18:06:08 +00004
Tom Stellard79243d92014-10-01 17:15:17 +00005; FUNC-LABEL: {{^}}fmul_f32:
Matt Arsenault2b252ec2014-07-28 18:06:08 +00006; R600: MUL_IEEE {{\** *}}{{T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W
7
8; SI: V_MUL_F32
Tom Stellarda92ff872013-08-16 23:51:24 +00009define void @fmul_f32(float addrspace(1)* %out, float %a, float %b) {
10entry:
11 %0 = fmul float %a, %b
12 store float %0, float addrspace(1)* %out
13 ret void
Tom Stellard75aadc22012-12-11 21:25:42 +000014}
15
16declare float @llvm.R600.load.input(i32) readnone
17
18declare void @llvm.AMDGPU.store.output(float, i32)
19
Tom Stellard79243d92014-10-01 17:15:17 +000020; FUNC-LABEL: {{^}}fmul_v2f32:
Matt Arsenault2b252ec2014-07-28 18:06:08 +000021; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}
22; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}
23
24; SI: V_MUL_F32
25; SI: V_MUL_F32
Tom Stellard0344cdf2013-08-01 15:23:42 +000026define void @fmul_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) {
27entry:
28 %0 = fmul <2 x float> %a, %b
29 store <2 x float> %0, <2 x float> addrspace(1)* %out
30 ret void
31}
32
Tom Stellard79243d92014-10-01 17:15:17 +000033; FUNC-LABEL: {{^}}fmul_v4f32:
Matt Arsenault2b252ec2014-07-28 18:06:08 +000034; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
35; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
36; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
37; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
38
39; SI: V_MUL_F32
40; SI: V_MUL_F32
41; SI: V_MUL_F32
42; SI: V_MUL_F32
Tom Stellard5a6b0d82013-04-19 02:10:53 +000043define void @fmul_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
44 %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
45 %a = load <4 x float> addrspace(1) * %in
46 %b = load <4 x float> addrspace(1) * %b_ptr
47 %result = fmul <4 x float> %a, %b
48 store <4 x float> %result, <4 x float> addrspace(1)* %out
49 ret void
50}
Matt Arsenaultc1a71212014-09-02 19:02:53 +000051
Tom Stellard79243d92014-10-01 17:15:17 +000052; FUNC-LABEL: {{^}}test_mul_2_k:
Matt Arsenaultc1a71212014-09-02 19:02:53 +000053; SI: V_MUL_F32
54; SI-NOT: V_MUL_F32
55; SI: S_ENDPGM
56define void @test_mul_2_k(float addrspace(1)* %out, float %x) #0 {
57 %y = fmul float %x, 2.0
58 %z = fmul float %y, 3.0
59 store float %z, float addrspace(1)* %out
60 ret void
61}
62
Tom Stellard79243d92014-10-01 17:15:17 +000063; FUNC-LABEL: {{^}}test_mul_2_k_inv:
Matt Arsenaultc1a71212014-09-02 19:02:53 +000064; SI: V_MUL_F32
65; SI-NOT: V_MUL_F32
66; SI-NOT: V_MAD_F32
67; SI: S_ENDPGM
68define void @test_mul_2_k_inv(float addrspace(1)* %out, float %x) #0 {
69 %y = fmul float %x, 3.0
70 %z = fmul float %y, 2.0
71 store float %z, float addrspace(1)* %out
72 ret void
73}
74
75attributes #0 = { "less-precise-fpmad"="true" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "unsafe-fp-math"="true" }