| Nicolai Haehnle | 87bc4c2 | 2016-10-07 08:40:14 +0000 | [diff] [blame] | 1 | ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s |
| Matt Arsenault | 7aad8fd | 2017-01-24 22:02:15 +0000 | [diff] [blame^] | 2 | ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s |
| Nicolai Haehnle | 87bc4c2 | 2016-10-07 08:40:14 +0000 | [diff] [blame] | 3 | |
| 4 | ; This used to crash because during intermediate control flow lowering, there |
| 5 | ; was a sequence |
| 6 | ; s_mov_b64 s[0:1], exec |
| 7 | ; s_and_b64 s[2:3], s[0:1], s[2:3] ; def & use of the same register pair |
| 8 | ; ... |
| 9 | ; s_mov_b64_term exec, s[2:3] |
| 10 | ; that was not treated correctly. |
| 11 | ; |
| 12 | ; GCN-LABEL: {{^}}ham: |
| 13 | ; GCN-DAG: v_cmp_lt_f32_e64 [[OTHERCC:s\[[0-9]+:[0-9]+\]]], |
| 14 | ; GCN-DAG: v_cmp_lt_f32_e32 vcc, |
| 15 | ; GCN: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[OTHERCC]] |
| 16 | ; GCN: s_and_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]], [[AND]] |
| Stanislav Mekhanoshin | ae0f6620 | 2016-11-22 01:42:34 +0000 | [diff] [blame] | 17 | ; GCN: s_xor_b64 {{s\[[0-9]+:[0-9]+\]}}, exec, [[SAVED]] |
| Nicolai Haehnle | 87bc4c2 | 2016-10-07 08:40:14 +0000 | [diff] [blame] | 18 | ; |
| 19 | ; TODO: The following sequence is a bug (missing s_endpgm)! |
| 20 | ; |
| 21 | ; GCN: s_branch [[BB:BB[0-9]+_[0-9]+]] |
| 22 | ; GCN: [[BB]]: |
| 23 | ; GCN-NEXT: .Lfunc_end0: |
| 24 | define amdgpu_ps void @ham(float %arg, float %arg1) #0 { |
| 25 | bb: |
| 26 | %tmp = fcmp ogt float %arg, 0.000000e+00 |
| 27 | %tmp2 = fcmp ogt float %arg1, 0.000000e+00 |
| 28 | %tmp3 = and i1 %tmp, %tmp2 |
| 29 | br i1 %tmp3, label %bb4, label %bb5 |
| 30 | |
| 31 | bb4: ; preds = %bb |
| 32 | unreachable |
| 33 | |
| 34 | bb5: ; preds = %bb |
| 35 | ret void |
| 36 | } |
| 37 | |
| 38 | attributes #0 = { nounwind readonly "InitialPSInputAddr"="36983" } |
| 39 | attributes #1 = { nounwind readnone } |