| Matt Arsenault | 7aad8fd | 2017-01-24 22:02:15 +0000 | [diff] [blame^] | 1 | ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s |
| 2 | ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s |
| Nicolai Haehnle | e2dda4f | 2016-04-19 21:58:22 +0000 | [diff] [blame] | 3 | |
| 4 | ; CHECK-LABEL: {{^}}main: |
| 5 | ; |
| 6 | ; Test for compilation only. This generated an invalid machine instruction |
| 7 | ; by trying to commute the operands of a V_CMP_EQ_i32_e32 instruction, both |
| 8 | ; of which were in SGPRs. |
| 9 | define amdgpu_vs float @main(i32 %v) { |
| 10 | main_body: |
| 11 | %d1 = call float @llvm.SI.load.const(<16 x i8> undef, i32 960) |
| 12 | %d2 = call float @llvm.SI.load.const(<16 x i8> undef, i32 976) |
| 13 | br i1 undef, label %ENDIF56, label %IF57 |
| 14 | |
| 15 | IF57: ; preds = %ENDIF |
| 16 | %v.1 = mul i32 %v, 2 |
| 17 | br label %ENDIF56 |
| 18 | |
| 19 | ENDIF56: ; preds = %IF57, %ENDIF |
| 20 | %v.2 = phi i32 [ %v, %main_body ], [ %v.1, %IF57 ] |
| 21 | %d1.i = bitcast float %d1 to i32 |
| 22 | %cc1 = icmp eq i32 %d1.i, 0 |
| 23 | br i1 %cc1, label %ENDIF59, label %IF60 |
| 24 | |
| 25 | IF60: ; preds = %ENDIF56 |
| 26 | %v.3 = mul i32 %v.2, 2 |
| 27 | br label %ENDIF59 |
| 28 | |
| 29 | ENDIF59: ; preds = %IF60, %ENDIF56 |
| 30 | %v.4 = phi i32 [ %v.2, %ENDIF56 ], [ %v.3, %IF60 ] |
| 31 | %d2.i = bitcast float %d2 to i32 |
| 32 | %cc2 = icmp eq i32 %d2.i, 0 |
| 33 | br i1 %cc2, label %ENDIF62, label %IF63 |
| 34 | |
| 35 | IF63: ; preds = %ENDIF59 |
| 36 | unreachable |
| 37 | |
| 38 | ENDIF62: ; preds = %ENDIF59 |
| 39 | %r = bitcast i32 %v.4 to float |
| 40 | ret float %r |
| 41 | } |
| 42 | |
| 43 | ; Function Attrs: nounwind readnone |
| 44 | declare float @llvm.SI.load.const(<16 x i8>, i32) #0 |
| 45 | |
| 46 | attributes #0 = { nounwind readnone } |
| 47 | attributes #1 = { readnone } |