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gerrit-public.fairphone.software / toolchain / llvm-project / 7d6aa1f7ae73206460bc36c97d5b48bdbf7c2cd8 / . / llvm / test / CodeGen / RISCV / vararg.ll
blob: 61a6178e09587e66ac163f6537e97408eb38fbc1 [file] [log] [blame]
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]3; RUN: | FileCheck -check-prefix=RV32I-FPELIM %s
4; RUN: llc -mtriple=riscv32 -verify-machineinstrs -disable-fp-elim < %s \
5; RUN: | FileCheck -check-prefix=RV32I-WITHFP %s
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]6
7declare void @llvm.va_start(i8*)
8declare void @llvm.va_end(i8*)
9
10declare void @notdead(i8*)
11
12; Although frontends are recommended to not generate va_arg due to the lack of
13; support for aggregate types, we test simple cases here to ensure they are
14; lowered correctly
15
16define i32 @va1(i8* %fmt, ...) nounwind {
17; RV32I-LABEL: va1:
18; RV32I: # %bb.0:
19; RV32I-NEXT: addi sp, sp, -48
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]20; RV32I-NEXT: sw a1, 20(sp)
21; RV32I-NEXT: sw a7, 44(sp)
22; RV32I-NEXT: sw a6, 40(sp)
23; RV32I-NEXT: sw a5, 36(sp)
24; RV32I-NEXT: sw a4, 32(sp)
25; RV32I-NEXT: sw a3, 28(sp)
26; RV32I-NEXT: sw a2, 24(sp)
27; RV32I-NEXT: addi a0, sp, 24
28; RV32I-NEXT: sw a0, 12(sp)
29; RV32I-NEXT: lw a0, 20(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]30; RV32I-NEXT: addi sp, sp, 48
31; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]32; RV32I-FPELIM-LABEL: va1:
33; RV32I-FPELIM: # %bb.0:
34; RV32I-FPELIM-NEXT: addi sp, sp, -48
35; RV32I-FPELIM-NEXT: sw a1, 20(sp)
36; RV32I-FPELIM-NEXT: sw a7, 44(sp)
37; RV32I-FPELIM-NEXT: sw a6, 40(sp)
38; RV32I-FPELIM-NEXT: sw a5, 36(sp)
39; RV32I-FPELIM-NEXT: sw a4, 32(sp)
40; RV32I-FPELIM-NEXT: sw a3, 28(sp)
41; RV32I-FPELIM-NEXT: sw a2, 24(sp)
42; RV32I-FPELIM-NEXT: addi a0, sp, 24
43; RV32I-FPELIM-NEXT: sw a0, 12(sp)
44; RV32I-FPELIM-NEXT: lw a0, 20(sp)
45; RV32I-FPELIM-NEXT: addi sp, sp, 48
46; RV32I-FPELIM-NEXT: ret
47;
48; RV32I-WITHFP-LABEL: va1:
49; RV32I-WITHFP: # %bb.0:
50; RV32I-WITHFP-NEXT: addi sp, sp, -48
51; RV32I-WITHFP-NEXT: sw ra, 12(sp)
52; RV32I-WITHFP-NEXT: sw s0, 8(sp)
53; RV32I-WITHFP-NEXT: addi s0, sp, 16
54; RV32I-WITHFP-NEXT: sw a1, 4(s0)
55; RV32I-WITHFP-NEXT: sw a7, 28(s0)
56; RV32I-WITHFP-NEXT: sw a6, 24(s0)
57; RV32I-WITHFP-NEXT: sw a5, 20(s0)
58; RV32I-WITHFP-NEXT: sw a4, 16(s0)
59; RV32I-WITHFP-NEXT: sw a3, 12(s0)
60; RV32I-WITHFP-NEXT: sw a2, 8(s0)
61; RV32I-WITHFP-NEXT: addi a0, s0, 8
62; RV32I-WITHFP-NEXT: sw a0, -12(s0)
63; RV32I-WITHFP-NEXT: lw a0, 4(s0)
64; RV32I-WITHFP-NEXT: lw s0, 8(sp)
65; RV32I-WITHFP-NEXT: lw ra, 12(sp)
66; RV32I-WITHFP-NEXT: addi sp, sp, 48
67; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]68 %va = alloca i8*, align 4
69 %1 = bitcast i8** %va to i8*
70 call void @llvm.va_start(i8* %1)
71 %argp.cur = load i8*, i8** %va, align 4
72 %argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 4
73 store i8* %argp.next, i8** %va, align 4
74 %2 = bitcast i8* %argp.cur to i32*
75 %3 = load i32, i32* %2, align 4
76 call void @llvm.va_end(i8* %1)
77 ret i32 %3
78}
79
80define i32 @va1_va_arg(i8* %fmt, ...) nounwind {
81; RV32I-LABEL: va1_va_arg:
82; RV32I: # %bb.0:
83; RV32I-NEXT: addi sp, sp, -48
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]84; RV32I-NEXT: sw a1, 20(sp)
85; RV32I-NEXT: sw a7, 44(sp)
86; RV32I-NEXT: sw a6, 40(sp)
87; RV32I-NEXT: sw a5, 36(sp)
88; RV32I-NEXT: sw a4, 32(sp)
89; RV32I-NEXT: sw a3, 28(sp)
90; RV32I-NEXT: sw a2, 24(sp)
91; RV32I-NEXT: addi a0, sp, 24
92; RV32I-NEXT: sw a0, 12(sp)
93; RV32I-NEXT: lw a0, 20(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]94; RV32I-NEXT: addi sp, sp, 48
95; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]96; RV32I-FPELIM-LABEL: va1_va_arg:
97; RV32I-FPELIM: # %bb.0:
98; RV32I-FPELIM-NEXT: addi sp, sp, -48
99; RV32I-FPELIM-NEXT: sw a1, 20(sp)
100; RV32I-FPELIM-NEXT: sw a7, 44(sp)
101; RV32I-FPELIM-NEXT: sw a6, 40(sp)
102; RV32I-FPELIM-NEXT: sw a5, 36(sp)
103; RV32I-FPELIM-NEXT: sw a4, 32(sp)
104; RV32I-FPELIM-NEXT: sw a3, 28(sp)
105; RV32I-FPELIM-NEXT: sw a2, 24(sp)
106; RV32I-FPELIM-NEXT: addi a0, sp, 24
107; RV32I-FPELIM-NEXT: sw a0, 12(sp)
108; RV32I-FPELIM-NEXT: lw a0, 20(sp)
109; RV32I-FPELIM-NEXT: addi sp, sp, 48
110; RV32I-FPELIM-NEXT: ret
111;
112; RV32I-WITHFP-LABEL: va1_va_arg:
113; RV32I-WITHFP: # %bb.0:
114; RV32I-WITHFP-NEXT: addi sp, sp, -48
115; RV32I-WITHFP-NEXT: sw ra, 12(sp)
116; RV32I-WITHFP-NEXT: sw s0, 8(sp)
117; RV32I-WITHFP-NEXT: addi s0, sp, 16
118; RV32I-WITHFP-NEXT: sw a1, 4(s0)
119; RV32I-WITHFP-NEXT: sw a7, 28(s0)
120; RV32I-WITHFP-NEXT: sw a6, 24(s0)
121; RV32I-WITHFP-NEXT: sw a5, 20(s0)
122; RV32I-WITHFP-NEXT: sw a4, 16(s0)
123; RV32I-WITHFP-NEXT: sw a3, 12(s0)
124; RV32I-WITHFP-NEXT: sw a2, 8(s0)
125; RV32I-WITHFP-NEXT: addi a0, s0, 8
126; RV32I-WITHFP-NEXT: sw a0, -12(s0)
127; RV32I-WITHFP-NEXT: lw a0, 4(s0)
128; RV32I-WITHFP-NEXT: lw s0, 8(sp)
129; RV32I-WITHFP-NEXT: lw ra, 12(sp)
130; RV32I-WITHFP-NEXT: addi sp, sp, 48
131; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]132 %va = alloca i8*, align 4
133 %1 = bitcast i8** %va to i8*
134 call void @llvm.va_start(i8* %1)
135 %2 = va_arg i8** %va, i32
136 call void @llvm.va_end(i8* %1)
137 ret i32 %2
138}
139
140; Ensure the adjustment when restoring the stack pointer using the frame
141; pointer is correct
142define i32 @va1_va_arg_alloca(i8* %fmt, ...) nounwind {
143; RV32I-LABEL: va1_va_arg_alloca:
144; RV32I: # %bb.0:
145; RV32I-NEXT: addi sp, sp, -48
146; RV32I-NEXT: sw ra, 12(sp)
147; RV32I-NEXT: sw s0, 8(sp)
148; RV32I-NEXT: sw s1, 4(sp)
149; RV32I-NEXT: addi s0, sp, 16
150; RV32I-NEXT: sw a1, 4(s0)
151; RV32I-NEXT: sw a7, 28(s0)
152; RV32I-NEXT: sw a6, 24(s0)
153; RV32I-NEXT: sw a5, 20(s0)
154; RV32I-NEXT: sw a4, 16(s0)
155; RV32I-NEXT: sw a3, 12(s0)
156; RV32I-NEXT: sw a2, 8(s0)
157; RV32I-NEXT: addi a0, s0, 8
158; RV32I-NEXT: sw a0, -16(s0)
159; RV32I-NEXT: lw s1, 4(s0)
160; RV32I-NEXT: addi a0, s1, 15
161; RV32I-NEXT: andi a0, a0, -16
162; RV32I-NEXT: sub a0, sp, a0
163; RV32I-NEXT: mv sp, a0
164; RV32I-NEXT: lui a1, %hi(notdead)
165; RV32I-NEXT: addi a1, a1, %lo(notdead)
166; RV32I-NEXT: jalr a1
167; RV32I-NEXT: mv a0, s1
168; RV32I-NEXT: addi sp, s0, -16
169; RV32I-NEXT: lw s1, 4(sp)
170; RV32I-NEXT: lw s0, 8(sp)
171; RV32I-NEXT: lw ra, 12(sp)
172; RV32I-NEXT: addi sp, sp, 48
173; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]174; RV32I-FPELIM-LABEL: va1_va_arg_alloca:
175; RV32I-FPELIM: # %bb.0:
176; RV32I-FPELIM-NEXT: addi sp, sp, -48
177; RV32I-FPELIM-NEXT: sw ra, 12(sp)
178; RV32I-FPELIM-NEXT: sw s0, 8(sp)
179; RV32I-FPELIM-NEXT: sw s1, 4(sp)
180; RV32I-FPELIM-NEXT: addi s0, sp, 16
181; RV32I-FPELIM-NEXT: sw a1, 4(s0)
182; RV32I-FPELIM-NEXT: sw a7, 28(s0)
183; RV32I-FPELIM-NEXT: sw a6, 24(s0)
184; RV32I-FPELIM-NEXT: sw a5, 20(s0)
185; RV32I-FPELIM-NEXT: sw a4, 16(s0)
186; RV32I-FPELIM-NEXT: sw a3, 12(s0)
187; RV32I-FPELIM-NEXT: sw a2, 8(s0)
188; RV32I-FPELIM-NEXT: addi a0, s0, 8
189; RV32I-FPELIM-NEXT: sw a0, -16(s0)
190; RV32I-FPELIM-NEXT: lw s1, 4(s0)
191; RV32I-FPELIM-NEXT: addi a0, s1, 15
192; RV32I-FPELIM-NEXT: andi a0, a0, -16
193; RV32I-FPELIM-NEXT: sub a0, sp, a0
194; RV32I-FPELIM-NEXT: mv sp, a0
195; RV32I-FPELIM-NEXT: lui a1, %hi(notdead)
196; RV32I-FPELIM-NEXT: addi a1, a1, %lo(notdead)
197; RV32I-FPELIM-NEXT: jalr a1
198; RV32I-FPELIM-NEXT: mv a0, s1
199; RV32I-FPELIM-NEXT: addi sp, s0, -16
200; RV32I-FPELIM-NEXT: lw s1, 4(sp)
201; RV32I-FPELIM-NEXT: lw s0, 8(sp)
202; RV32I-FPELIM-NEXT: lw ra, 12(sp)
203; RV32I-FPELIM-NEXT: addi sp, sp, 48
204; RV32I-FPELIM-NEXT: ret
205;
206; RV32I-WITHFP-LABEL: va1_va_arg_alloca:
207; RV32I-WITHFP: # %bb.0:
208; RV32I-WITHFP-NEXT: addi sp, sp, -48
209; RV32I-WITHFP-NEXT: sw ra, 12(sp)
210; RV32I-WITHFP-NEXT: sw s0, 8(sp)
211; RV32I-WITHFP-NEXT: sw s1, 4(sp)
212; RV32I-WITHFP-NEXT: addi s0, sp, 16
213; RV32I-WITHFP-NEXT: sw a1, 4(s0)
214; RV32I-WITHFP-NEXT: sw a7, 28(s0)
215; RV32I-WITHFP-NEXT: sw a6, 24(s0)
216; RV32I-WITHFP-NEXT: sw a5, 20(s0)
217; RV32I-WITHFP-NEXT: sw a4, 16(s0)
218; RV32I-WITHFP-NEXT: sw a3, 12(s0)
219; RV32I-WITHFP-NEXT: sw a2, 8(s0)
220; RV32I-WITHFP-NEXT: addi a0, s0, 8
221; RV32I-WITHFP-NEXT: sw a0, -16(s0)
222; RV32I-WITHFP-NEXT: lw s1, 4(s0)
223; RV32I-WITHFP-NEXT: addi a0, s1, 15
224; RV32I-WITHFP-NEXT: andi a0, a0, -16
225; RV32I-WITHFP-NEXT: sub a0, sp, a0
226; RV32I-WITHFP-NEXT: mv sp, a0
227; RV32I-WITHFP-NEXT: lui a1, %hi(notdead)
228; RV32I-WITHFP-NEXT: addi a1, a1, %lo(notdead)
229; RV32I-WITHFP-NEXT: jalr a1
230; RV32I-WITHFP-NEXT: mv a0, s1
231; RV32I-WITHFP-NEXT: addi sp, s0, -16
232; RV32I-WITHFP-NEXT: lw s1, 4(sp)
233; RV32I-WITHFP-NEXT: lw s0, 8(sp)
234; RV32I-WITHFP-NEXT: lw ra, 12(sp)
235; RV32I-WITHFP-NEXT: addi sp, sp, 48
236; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]237 %va = alloca i8*, align 4
238 %1 = bitcast i8** %va to i8*
239 call void @llvm.va_start(i8* %1)
240 %2 = va_arg i8** %va, i32
241 %3 = alloca i8, i32 %2
242 call void @notdead(i8* %3)
243 call void @llvm.va_end(i8* %1)
244 ret i32 %2
245}
246
247define void @va1_caller() nounwind {
248; RV32I-LABEL: va1_caller:
249; RV32I: # %bb.0:
250; RV32I-NEXT: addi sp, sp, -16
251; RV32I-NEXT: sw ra, 12(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]252; RV32I-NEXT: lui a0, 261888
253; RV32I-NEXT: mv a3, a0
254; RV32I-NEXT: lui a0, %hi(va1)
255; RV32I-NEXT: addi a0, a0, %lo(va1)
256; RV32I-NEXT: addi a4, zero, 2
257; RV32I-NEXT: mv a2, zero
258; RV32I-NEXT: jalr a0
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]259; RV32I-NEXT: lw ra, 12(sp)
260; RV32I-NEXT: addi sp, sp, 16
261; RV32I-NEXT: ret
262; Pass a double, as a float would be promoted by a C/C++ frontend
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]263; RV32I-FPELIM-LABEL: va1_caller:
264; RV32I-FPELIM: # %bb.0:
265; RV32I-FPELIM-NEXT: addi sp, sp, -16
266; RV32I-FPELIM-NEXT: sw ra, 12(sp)
267; RV32I-FPELIM-NEXT: lui a0, 261888
268; RV32I-FPELIM-NEXT: mv a3, a0
269; RV32I-FPELIM-NEXT: lui a0, %hi(va1)
270; RV32I-FPELIM-NEXT: addi a0, a0, %lo(va1)
271; RV32I-FPELIM-NEXT: addi a4, zero, 2
272; RV32I-FPELIM-NEXT: mv a2, zero
273; RV32I-FPELIM-NEXT: jalr a0
274; RV32I-FPELIM-NEXT: lw ra, 12(sp)
275; RV32I-FPELIM-NEXT: addi sp, sp, 16
276; RV32I-FPELIM-NEXT: ret
277;
278; RV32I-WITHFP-LABEL: va1_caller:
279; RV32I-WITHFP: # %bb.0:
280; RV32I-WITHFP-NEXT: addi sp, sp, -16
281; RV32I-WITHFP-NEXT: sw ra, 12(sp)
282; RV32I-WITHFP-NEXT: sw s0, 8(sp)
283; RV32I-WITHFP-NEXT: addi s0, sp, 16
284; RV32I-WITHFP-NEXT: lui a0, 261888
285; RV32I-WITHFP-NEXT: mv a3, a0
286; RV32I-WITHFP-NEXT: lui a0, %hi(va1)
287; RV32I-WITHFP-NEXT: addi a0, a0, %lo(va1)
288; RV32I-WITHFP-NEXT: addi a4, zero, 2
289; RV32I-WITHFP-NEXT: mv a2, zero
290; RV32I-WITHFP-NEXT: jalr a0
291; RV32I-WITHFP-NEXT: lw s0, 8(sp)
292; RV32I-WITHFP-NEXT: lw ra, 12(sp)
293; RV32I-WITHFP-NEXT: addi sp, sp, 16
294; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]295 %1 = call i32 (i8*, ...) @va1(i8* undef, double 1.0, i32 2)
296 ret void
297}
298
299; Ensure that 2x xlen size+alignment varargs are accessed via an "aligned"
300; register pair (where the first register is even-numbered).
301
302define double @va2(i8 *%fmt, ...) nounwind {
303; RV32I-LABEL: va2:
304; RV32I: # %bb.0:
305; RV32I-NEXT: addi sp, sp, -48
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]306; RV32I-NEXT: sw a7, 44(sp)
307; RV32I-NEXT: sw a6, 40(sp)
308; RV32I-NEXT: sw a5, 36(sp)
309; RV32I-NEXT: sw a4, 32(sp)
310; RV32I-NEXT: sw a3, 28(sp)
311; RV32I-NEXT: sw a2, 24(sp)
312; RV32I-NEXT: sw a1, 20(sp)
313; RV32I-NEXT: addi a0, sp, 35
314; RV32I-NEXT: sw a0, 12(sp)
315; RV32I-NEXT: addi a0, sp, 27
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]316; RV32I-NEXT: andi a1, a0, -8
317; RV32I-NEXT: lw a0, 0(a1)
318; RV32I-NEXT: ori a1, a1, 4
319; RV32I-NEXT: lw a1, 0(a1)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]320; RV32I-NEXT: addi sp, sp, 48
321; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]322; RV32I-FPELIM-LABEL: va2:
323; RV32I-FPELIM: # %bb.0:
324; RV32I-FPELIM-NEXT: addi sp, sp, -48
325; RV32I-FPELIM-NEXT: sw a7, 44(sp)
326; RV32I-FPELIM-NEXT: sw a6, 40(sp)
327; RV32I-FPELIM-NEXT: sw a5, 36(sp)
328; RV32I-FPELIM-NEXT: sw a4, 32(sp)
329; RV32I-FPELIM-NEXT: sw a3, 28(sp)
330; RV32I-FPELIM-NEXT: sw a2, 24(sp)
331; RV32I-FPELIM-NEXT: sw a1, 20(sp)
332; RV32I-FPELIM-NEXT: addi a0, sp, 35
333; RV32I-FPELIM-NEXT: sw a0, 12(sp)
334; RV32I-FPELIM-NEXT: addi a0, sp, 27
335; RV32I-FPELIM-NEXT: andi a1, a0, -8
336; RV32I-FPELIM-NEXT: lw a0, 0(a1)
337; RV32I-FPELIM-NEXT: ori a1, a1, 4
338; RV32I-FPELIM-NEXT: lw a1, 0(a1)
339; RV32I-FPELIM-NEXT: addi sp, sp, 48
340; RV32I-FPELIM-NEXT: ret
341;
342; RV32I-WITHFP-LABEL: va2:
343; RV32I-WITHFP: # %bb.0:
344; RV32I-WITHFP-NEXT: addi sp, sp, -48
345; RV32I-WITHFP-NEXT: sw ra, 12(sp)
346; RV32I-WITHFP-NEXT: sw s0, 8(sp)
347; RV32I-WITHFP-NEXT: addi s0, sp, 16
348; RV32I-WITHFP-NEXT: sw a7, 28(s0)
349; RV32I-WITHFP-NEXT: sw a6, 24(s0)
350; RV32I-WITHFP-NEXT: sw a5, 20(s0)
351; RV32I-WITHFP-NEXT: sw a4, 16(s0)
352; RV32I-WITHFP-NEXT: sw a3, 12(s0)
353; RV32I-WITHFP-NEXT: sw a2, 8(s0)
354; RV32I-WITHFP-NEXT: sw a1, 4(s0)
355; RV32I-WITHFP-NEXT: addi a0, s0, 19
356; RV32I-WITHFP-NEXT: sw a0, -12(s0)
357; RV32I-WITHFP-NEXT: addi a0, s0, 11
358; RV32I-WITHFP-NEXT: andi a1, a0, -8
359; RV32I-WITHFP-NEXT: lw a0, 0(a1)
360; RV32I-WITHFP-NEXT: ori a1, a1, 4
361; RV32I-WITHFP-NEXT: lw a1, 0(a1)
362; RV32I-WITHFP-NEXT: lw s0, 8(sp)
363; RV32I-WITHFP-NEXT: lw ra, 12(sp)
364; RV32I-WITHFP-NEXT: addi sp, sp, 48
365; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]366 %va = alloca i8*, align 4
367 %1 = bitcast i8** %va to i8*
368 call void @llvm.va_start(i8* %1)
369 %2 = bitcast i8** %va to i32*
370 %argp.cur = load i32, i32* %2, align 4
371 %3 = add i32 %argp.cur, 7
372 %4 = and i32 %3, -8
373 %argp.cur.aligned = inttoptr i32 %3 to i8*
374 %argp.next = getelementptr inbounds i8, i8* %argp.cur.aligned, i32 8
375 store i8* %argp.next, i8** %va, align 4
376 %5 = inttoptr i32 %4 to double*
377 %6 = load double, double* %5, align 8
378 call void @llvm.va_end(i8* %1)
379 ret double %6
380}
381
382define double @va2_va_arg(i8 *%fmt, ...) nounwind {
383; RV32I-LABEL: va2_va_arg:
384; RV32I: # %bb.0:
385; RV32I-NEXT: addi sp, sp, -48
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]386; RV32I-NEXT: sw a7, 44(sp)
387; RV32I-NEXT: sw a6, 40(sp)
388; RV32I-NEXT: sw a5, 36(sp)
389; RV32I-NEXT: sw a4, 32(sp)
390; RV32I-NEXT: sw a3, 28(sp)
391; RV32I-NEXT: sw a2, 24(sp)
392; RV32I-NEXT: sw a1, 20(sp)
393; RV32I-NEXT: addi a0, sp, 27
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]394; RV32I-NEXT: andi a0, a0, -8
395; RV32I-NEXT: ori a1, a0, 4
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]396; RV32I-NEXT: sw a1, 12(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]397; RV32I-NEXT: lw a0, 0(a0)
398; RV32I-NEXT: addi a2, a1, 4
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]399; RV32I-NEXT: sw a2, 12(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]400; RV32I-NEXT: lw a1, 0(a1)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]401; RV32I-NEXT: addi sp, sp, 48
402; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]403; RV32I-FPELIM-LABEL: va2_va_arg:
404; RV32I-FPELIM: # %bb.0:
405; RV32I-FPELIM-NEXT: addi sp, sp, -48
406; RV32I-FPELIM-NEXT: sw a7, 44(sp)
407; RV32I-FPELIM-NEXT: sw a6, 40(sp)
408; RV32I-FPELIM-NEXT: sw a5, 36(sp)
409; RV32I-FPELIM-NEXT: sw a4, 32(sp)
410; RV32I-FPELIM-NEXT: sw a3, 28(sp)
411; RV32I-FPELIM-NEXT: sw a2, 24(sp)
412; RV32I-FPELIM-NEXT: sw a1, 20(sp)
413; RV32I-FPELIM-NEXT: addi a0, sp, 27
414; RV32I-FPELIM-NEXT: andi a0, a0, -8
415; RV32I-FPELIM-NEXT: ori a1, a0, 4
416; RV32I-FPELIM-NEXT: sw a1, 12(sp)
417; RV32I-FPELIM-NEXT: lw a0, 0(a0)
418; RV32I-FPELIM-NEXT: addi a2, a1, 4
419; RV32I-FPELIM-NEXT: sw a2, 12(sp)
420; RV32I-FPELIM-NEXT: lw a1, 0(a1)
421; RV32I-FPELIM-NEXT: addi sp, sp, 48
422; RV32I-FPELIM-NEXT: ret
423;
424; RV32I-WITHFP-LABEL: va2_va_arg:
425; RV32I-WITHFP: # %bb.0:
426; RV32I-WITHFP-NEXT: addi sp, sp, -48
427; RV32I-WITHFP-NEXT: sw ra, 12(sp)
428; RV32I-WITHFP-NEXT: sw s0, 8(sp)
429; RV32I-WITHFP-NEXT: addi s0, sp, 16
430; RV32I-WITHFP-NEXT: sw a7, 28(s0)
431; RV32I-WITHFP-NEXT: sw a6, 24(s0)
432; RV32I-WITHFP-NEXT: sw a5, 20(s0)
433; RV32I-WITHFP-NEXT: sw a4, 16(s0)
434; RV32I-WITHFP-NEXT: sw a3, 12(s0)
435; RV32I-WITHFP-NEXT: sw a2, 8(s0)
436; RV32I-WITHFP-NEXT: sw a1, 4(s0)
437; RV32I-WITHFP-NEXT: addi a0, s0, 11
438; RV32I-WITHFP-NEXT: andi a0, a0, -8
439; RV32I-WITHFP-NEXT: ori a1, a0, 4
440; RV32I-WITHFP-NEXT: sw a1, -12(s0)
441; RV32I-WITHFP-NEXT: lw a0, 0(a0)
442; RV32I-WITHFP-NEXT: addi a2, a1, 4
443; RV32I-WITHFP-NEXT: sw a2, -12(s0)
444; RV32I-WITHFP-NEXT: lw a1, 0(a1)
445; RV32I-WITHFP-NEXT: lw s0, 8(sp)
446; RV32I-WITHFP-NEXT: lw ra, 12(sp)
447; RV32I-WITHFP-NEXT: addi sp, sp, 48
448; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]449 %va = alloca i8*, align 4
450 %1 = bitcast i8** %va to i8*
451 call void @llvm.va_start(i8* %1)
452 %2 = va_arg i8** %va, double
453 call void @llvm.va_end(i8* %1)
454 ret double %2
455}
456
457define void @va2_caller() nounwind {
458; RV32I-LABEL: va2_caller:
459; RV32I: # %bb.0:
460; RV32I-NEXT: addi sp, sp, -16
461; RV32I-NEXT: sw ra, 12(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]462; RV32I-NEXT: lui a0, 261888
463; RV32I-NEXT: mv a3, a0
464; RV32I-NEXT: lui a0, %hi(va2)
465; RV32I-NEXT: addi a0, a0, %lo(va2)
466; RV32I-NEXT: mv a2, zero
467; RV32I-NEXT: jalr a0
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]468; RV32I-NEXT: lw ra, 12(sp)
469; RV32I-NEXT: addi sp, sp, 16
470; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]471; RV32I-FPELIM-LABEL: va2_caller:
472; RV32I-FPELIM: # %bb.0:
473; RV32I-FPELIM-NEXT: addi sp, sp, -16
474; RV32I-FPELIM-NEXT: sw ra, 12(sp)
475; RV32I-FPELIM-NEXT: lui a0, 261888
476; RV32I-FPELIM-NEXT: mv a3, a0
477; RV32I-FPELIM-NEXT: lui a0, %hi(va2)
478; RV32I-FPELIM-NEXT: addi a0, a0, %lo(va2)
479; RV32I-FPELIM-NEXT: mv a2, zero
480; RV32I-FPELIM-NEXT: jalr a0
481; RV32I-FPELIM-NEXT: lw ra, 12(sp)
482; RV32I-FPELIM-NEXT: addi sp, sp, 16
483; RV32I-FPELIM-NEXT: ret
484;
485; RV32I-WITHFP-LABEL: va2_caller:
486; RV32I-WITHFP: # %bb.0:
487; RV32I-WITHFP-NEXT: addi sp, sp, -16
488; RV32I-WITHFP-NEXT: sw ra, 12(sp)
489; RV32I-WITHFP-NEXT: sw s0, 8(sp)
490; RV32I-WITHFP-NEXT: addi s0, sp, 16
491; RV32I-WITHFP-NEXT: lui a0, 261888
492; RV32I-WITHFP-NEXT: mv a3, a0
493; RV32I-WITHFP-NEXT: lui a0, %hi(va2)
494; RV32I-WITHFP-NEXT: addi a0, a0, %lo(va2)
495; RV32I-WITHFP-NEXT: mv a2, zero
496; RV32I-WITHFP-NEXT: jalr a0
497; RV32I-WITHFP-NEXT: lw s0, 8(sp)
498; RV32I-WITHFP-NEXT: lw ra, 12(sp)
499; RV32I-WITHFP-NEXT: addi sp, sp, 16
500; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]501 %1 = call double (i8*, ...) @va2(i8* undef, double 1.000000e+00)
502 ret void
503}
504
505; Ensure a named double argument is passed in a1 and a2, while the vararg
506; double is passed in a4 and a5 (rather than a3 and a4)
507
508define double @va3(i32 %a, double %b, ...) nounwind {
509; RV32I-LABEL: va3:
510; RV32I: # %bb.0:
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]511; RV32I-NEXT: addi sp, sp, -32
512; RV32I-NEXT: sw ra, 4(sp)
513; RV32I-NEXT: sw a7, 28(sp)
514; RV32I-NEXT: sw a6, 24(sp)
515; RV32I-NEXT: sw a5, 20(sp)
516; RV32I-NEXT: sw a4, 16(sp)
517; RV32I-NEXT: sw a3, 12(sp)
518; RV32I-NEXT: addi a0, sp, 27
519; RV32I-NEXT: sw a0, 0(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]520; RV32I-NEXT: lui a0, %hi(__adddf3)
521; RV32I-NEXT: addi a5, a0, %lo(__adddf3)
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]522; RV32I-NEXT: addi a0, sp, 19
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]523; RV32I-NEXT: andi a0, a0, -8
524; RV32I-NEXT: lw a4, 0(a0)
525; RV32I-NEXT: ori a0, a0, 4
526; RV32I-NEXT: lw a3, 0(a0)
527; RV32I-NEXT: mv a0, a1
528; RV32I-NEXT: mv a1, a2
529; RV32I-NEXT: mv a2, a4
530; RV32I-NEXT: jalr a5
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]531; RV32I-NEXT: lw ra, 4(sp)
532; RV32I-NEXT: addi sp, sp, 32
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]533; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]534; RV32I-FPELIM-LABEL: va3:
535; RV32I-FPELIM: # %bb.0:
536; RV32I-FPELIM-NEXT: addi sp, sp, -32
537; RV32I-FPELIM-NEXT: sw ra, 4(sp)
538; RV32I-FPELIM-NEXT: sw a7, 28(sp)
539; RV32I-FPELIM-NEXT: sw a6, 24(sp)
540; RV32I-FPELIM-NEXT: sw a5, 20(sp)
541; RV32I-FPELIM-NEXT: sw a4, 16(sp)
542; RV32I-FPELIM-NEXT: sw a3, 12(sp)
543; RV32I-FPELIM-NEXT: addi a0, sp, 27
544; RV32I-FPELIM-NEXT: sw a0, 0(sp)
545; RV32I-FPELIM-NEXT: lui a0, %hi(__adddf3)
546; RV32I-FPELIM-NEXT: addi a5, a0, %lo(__adddf3)
547; RV32I-FPELIM-NEXT: addi a0, sp, 19
548; RV32I-FPELIM-NEXT: andi a0, a0, -8
549; RV32I-FPELIM-NEXT: lw a4, 0(a0)
550; RV32I-FPELIM-NEXT: ori a0, a0, 4
551; RV32I-FPELIM-NEXT: lw a3, 0(a0)
552; RV32I-FPELIM-NEXT: mv a0, a1
553; RV32I-FPELIM-NEXT: mv a1, a2
554; RV32I-FPELIM-NEXT: mv a2, a4
555; RV32I-FPELIM-NEXT: jalr a5
556; RV32I-FPELIM-NEXT: lw ra, 4(sp)
557; RV32I-FPELIM-NEXT: addi sp, sp, 32
558; RV32I-FPELIM-NEXT: ret
559;
560; RV32I-WITHFP-LABEL: va3:
561; RV32I-WITHFP: # %bb.0:
562; RV32I-WITHFP-NEXT: addi sp, sp, -48
563; RV32I-WITHFP-NEXT: sw ra, 20(sp)
564; RV32I-WITHFP-NEXT: sw s0, 16(sp)
565; RV32I-WITHFP-NEXT: addi s0, sp, 24
566; RV32I-WITHFP-NEXT: sw a7, 20(s0)
567; RV32I-WITHFP-NEXT: sw a6, 16(s0)
568; RV32I-WITHFP-NEXT: sw a5, 12(s0)
569; RV32I-WITHFP-NEXT: sw a4, 8(s0)
570; RV32I-WITHFP-NEXT: sw a3, 4(s0)
571; RV32I-WITHFP-NEXT: addi a0, s0, 19
572; RV32I-WITHFP-NEXT: sw a0, -12(s0)
573; RV32I-WITHFP-NEXT: lui a0, %hi(__adddf3)
574; RV32I-WITHFP-NEXT: addi a5, a0, %lo(__adddf3)
575; RV32I-WITHFP-NEXT: addi a0, s0, 11
576; RV32I-WITHFP-NEXT: andi a0, a0, -8
577; RV32I-WITHFP-NEXT: lw a4, 0(a0)
578; RV32I-WITHFP-NEXT: ori a0, a0, 4
579; RV32I-WITHFP-NEXT: lw a3, 0(a0)
580; RV32I-WITHFP-NEXT: mv a0, a1
581; RV32I-WITHFP-NEXT: mv a1, a2
582; RV32I-WITHFP-NEXT: mv a2, a4
583; RV32I-WITHFP-NEXT: jalr a5
584; RV32I-WITHFP-NEXT: lw s0, 16(sp)
585; RV32I-WITHFP-NEXT: lw ra, 20(sp)
586; RV32I-WITHFP-NEXT: addi sp, sp, 48
587; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]588 %va = alloca i8*, align 4
589 %1 = bitcast i8** %va to i8*
590 call void @llvm.va_start(i8* %1)
591 %2 = bitcast i8** %va to i32*
592 %argp.cur = load i32, i32* %2, align 4
593 %3 = add i32 %argp.cur, 7
594 %4 = and i32 %3, -8
595 %argp.cur.aligned = inttoptr i32 %3 to i8*
596 %argp.next = getelementptr inbounds i8, i8* %argp.cur.aligned, i32 8
597 store i8* %argp.next, i8** %va, align 4
598 %5 = inttoptr i32 %4 to double*
599 %6 = load double, double* %5, align 8
600 call void @llvm.va_end(i8* %1)
601 %7 = fadd double %b, %6
602 ret double %7
603}
604
605define double @va3_va_arg(i32 %a, double %b, ...) nounwind {
606; RV32I-LABEL: va3_va_arg:
607; RV32I: # %bb.0:
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]608; RV32I-NEXT: addi sp, sp, -32
609; RV32I-NEXT: sw ra, 4(sp)
610; RV32I-NEXT: sw a7, 28(sp)
611; RV32I-NEXT: sw a6, 24(sp)
612; RV32I-NEXT: sw a5, 20(sp)
613; RV32I-NEXT: sw a4, 16(sp)
614; RV32I-NEXT: sw a3, 12(sp)
615; RV32I-NEXT: addi a0, sp, 19
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]616; RV32I-NEXT: andi a0, a0, -8
617; RV32I-NEXT: ori a3, a0, 4
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]618; RV32I-NEXT: sw a3, 0(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]619; RV32I-NEXT: lw a4, 0(a0)
620; RV32I-NEXT: addi a0, a3, 4
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]621; RV32I-NEXT: sw a0, 0(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]622; RV32I-NEXT: lui a0, %hi(__adddf3)
623; RV32I-NEXT: addi a5, a0, %lo(__adddf3)
624; RV32I-NEXT: lw a3, 0(a3)
625; RV32I-NEXT: mv a0, a1
626; RV32I-NEXT: mv a1, a2
627; RV32I-NEXT: mv a2, a4
628; RV32I-NEXT: jalr a5
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]629; RV32I-NEXT: lw ra, 4(sp)
630; RV32I-NEXT: addi sp, sp, 32
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]631; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]632; RV32I-FPELIM-LABEL: va3_va_arg:
633; RV32I-FPELIM: # %bb.0:
634; RV32I-FPELIM-NEXT: addi sp, sp, -32
635; RV32I-FPELIM-NEXT: sw ra, 4(sp)
636; RV32I-FPELIM-NEXT: sw a7, 28(sp)
637; RV32I-FPELIM-NEXT: sw a6, 24(sp)
638; RV32I-FPELIM-NEXT: sw a5, 20(sp)
639; RV32I-FPELIM-NEXT: sw a4, 16(sp)
640; RV32I-FPELIM-NEXT: sw a3, 12(sp)
641; RV32I-FPELIM-NEXT: addi a0, sp, 19
642; RV32I-FPELIM-NEXT: andi a0, a0, -8
643; RV32I-FPELIM-NEXT: ori a3, a0, 4
644; RV32I-FPELIM-NEXT: sw a3, 0(sp)
645; RV32I-FPELIM-NEXT: lw a4, 0(a0)
646; RV32I-FPELIM-NEXT: addi a0, a3, 4
647; RV32I-FPELIM-NEXT: sw a0, 0(sp)
648; RV32I-FPELIM-NEXT: lui a0, %hi(__adddf3)
649; RV32I-FPELIM-NEXT: addi a5, a0, %lo(__adddf3)
650; RV32I-FPELIM-NEXT: lw a3, 0(a3)
651; RV32I-FPELIM-NEXT: mv a0, a1
652; RV32I-FPELIM-NEXT: mv a1, a2
653; RV32I-FPELIM-NEXT: mv a2, a4
654; RV32I-FPELIM-NEXT: jalr a5
655; RV32I-FPELIM-NEXT: lw ra, 4(sp)
656; RV32I-FPELIM-NEXT: addi sp, sp, 32
657; RV32I-FPELIM-NEXT: ret
658;
659; RV32I-WITHFP-LABEL: va3_va_arg:
660; RV32I-WITHFP: # %bb.0:
661; RV32I-WITHFP-NEXT: addi sp, sp, -48
662; RV32I-WITHFP-NEXT: sw ra, 20(sp)
663; RV32I-WITHFP-NEXT: sw s0, 16(sp)
664; RV32I-WITHFP-NEXT: addi s0, sp, 24
665; RV32I-WITHFP-NEXT: sw a7, 20(s0)
666; RV32I-WITHFP-NEXT: sw a6, 16(s0)
667; RV32I-WITHFP-NEXT: sw a5, 12(s0)
668; RV32I-WITHFP-NEXT: sw a4, 8(s0)
669; RV32I-WITHFP-NEXT: sw a3, 4(s0)
670; RV32I-WITHFP-NEXT: addi a0, s0, 11
671; RV32I-WITHFP-NEXT: andi a0, a0, -8
672; RV32I-WITHFP-NEXT: ori a3, a0, 4
673; RV32I-WITHFP-NEXT: sw a3, -12(s0)
674; RV32I-WITHFP-NEXT: lw a4, 0(a0)
675; RV32I-WITHFP-NEXT: addi a0, a3, 4
676; RV32I-WITHFP-NEXT: sw a0, -12(s0)
677; RV32I-WITHFP-NEXT: lui a0, %hi(__adddf3)
678; RV32I-WITHFP-NEXT: addi a5, a0, %lo(__adddf3)
679; RV32I-WITHFP-NEXT: lw a3, 0(a3)
680; RV32I-WITHFP-NEXT: mv a0, a1
681; RV32I-WITHFP-NEXT: mv a1, a2
682; RV32I-WITHFP-NEXT: mv a2, a4
683; RV32I-WITHFP-NEXT: jalr a5
684; RV32I-WITHFP-NEXT: lw s0, 16(sp)
685; RV32I-WITHFP-NEXT: lw ra, 20(sp)
686; RV32I-WITHFP-NEXT: addi sp, sp, 48
687; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]688 %va = alloca i8*, align 4
689 %1 = bitcast i8** %va to i8*
690 call void @llvm.va_start(i8* %1)
691 %2 = va_arg i8** %va, double
692 call void @llvm.va_end(i8* %1)
693 %3 = fadd double %b, %2
694 ret double %3
695}
696
697define void @va3_caller() nounwind {
698; RV32I-LABEL: va3_caller:
699; RV32I: # %bb.0:
700; RV32I-NEXT: addi sp, sp, -16
701; RV32I-NEXT: sw ra, 12(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]702; RV32I-NEXT: lui a0, 261888
703; RV32I-NEXT: mv a2, a0
704; RV32I-NEXT: lui a0, 262144
705; RV32I-NEXT: mv a5, a0
706; RV32I-NEXT: lui a0, %hi(va3)
707; RV32I-NEXT: addi a3, a0, %lo(va3)
708; RV32I-NEXT: addi a0, zero, 2
709; RV32I-NEXT: mv a1, zero
710; RV32I-NEXT: mv a4, zero
711; RV32I-NEXT: jalr a3
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]712; RV32I-NEXT: lw ra, 12(sp)
713; RV32I-NEXT: addi sp, sp, 16
714; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]715; RV32I-FPELIM-LABEL: va3_caller:
716; RV32I-FPELIM: # %bb.0:
717; RV32I-FPELIM-NEXT: addi sp, sp, -16
718; RV32I-FPELIM-NEXT: sw ra, 12(sp)
719; RV32I-FPELIM-NEXT: lui a0, 261888
720; RV32I-FPELIM-NEXT: mv a2, a0
721; RV32I-FPELIM-NEXT: lui a0, 262144
722; RV32I-FPELIM-NEXT: mv a5, a0
723; RV32I-FPELIM-NEXT: lui a0, %hi(va3)
724; RV32I-FPELIM-NEXT: addi a3, a0, %lo(va3)
725; RV32I-FPELIM-NEXT: addi a0, zero, 2
726; RV32I-FPELIM-NEXT: mv a1, zero
727; RV32I-FPELIM-NEXT: mv a4, zero
728; RV32I-FPELIM-NEXT: jalr a3
729; RV32I-FPELIM-NEXT: lw ra, 12(sp)
730; RV32I-FPELIM-NEXT: addi sp, sp, 16
731; RV32I-FPELIM-NEXT: ret
732;
733; RV32I-WITHFP-LABEL: va3_caller:
734; RV32I-WITHFP: # %bb.0:
735; RV32I-WITHFP-NEXT: addi sp, sp, -16
736; RV32I-WITHFP-NEXT: sw ra, 12(sp)
737; RV32I-WITHFP-NEXT: sw s0, 8(sp)
738; RV32I-WITHFP-NEXT: addi s0, sp, 16
739; RV32I-WITHFP-NEXT: lui a0, 261888
740; RV32I-WITHFP-NEXT: mv a2, a0
741; RV32I-WITHFP-NEXT: lui a0, 262144
742; RV32I-WITHFP-NEXT: mv a5, a0
743; RV32I-WITHFP-NEXT: lui a0, %hi(va3)
744; RV32I-WITHFP-NEXT: addi a3, a0, %lo(va3)
745; RV32I-WITHFP-NEXT: addi a0, zero, 2
746; RV32I-WITHFP-NEXT: mv a1, zero
747; RV32I-WITHFP-NEXT: mv a4, zero
748; RV32I-WITHFP-NEXT: jalr a3
749; RV32I-WITHFP-NEXT: lw s0, 8(sp)
750; RV32I-WITHFP-NEXT: lw ra, 12(sp)
751; RV32I-WITHFP-NEXT: addi sp, sp, 16
752; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]753 %1 = call double (i32, double, ...) @va3(i32 2, double 1.000000e+00, double 2.000000e+00)
754 ret void
755}
756
757declare void @llvm.va_copy(i8*, i8*)
758
759define i32 @va4_va_copy(i32 %argno, ...) nounwind {
760; RV32I-LABEL: va4_va_copy:
761; RV32I: # %bb.0:
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]762; RV32I-NEXT: addi sp, sp, -48
763; RV32I-NEXT: sw ra, 12(sp)
764; RV32I-NEXT: sw s1, 8(sp)
765; RV32I-NEXT: sw a1, 20(sp)
766; RV32I-NEXT: sw a7, 44(sp)
767; RV32I-NEXT: sw a6, 40(sp)
768; RV32I-NEXT: sw a5, 36(sp)
769; RV32I-NEXT: sw a4, 32(sp)
770; RV32I-NEXT: sw a3, 28(sp)
771; RV32I-NEXT: sw a2, 24(sp)
772; RV32I-NEXT: addi a0, sp, 24
773; RV32I-NEXT: sw a0, 4(sp)
774; RV32I-NEXT: sw a0, 0(sp)
775; RV32I-NEXT: lw s1, 20(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]776; RV32I-NEXT: lui a1, %hi(notdead)
777; RV32I-NEXT: addi a1, a1, %lo(notdead)
778; RV32I-NEXT: jalr a1
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]779; RV32I-NEXT: lw a0, 4(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]780; RV32I-NEXT: addi a0, a0, 3
781; RV32I-NEXT: andi a0, a0, -4
782; RV32I-NEXT: addi a1, a0, 4
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]783; RV32I-NEXT: sw a1, 4(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]784; RV32I-NEXT: lw a1, 0(a0)
785; RV32I-NEXT: addi a0, a0, 7
786; RV32I-NEXT: andi a0, a0, -4
787; RV32I-NEXT: addi a2, a0, 4
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]788; RV32I-NEXT: sw a2, 4(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]789; RV32I-NEXT: lw a2, 0(a0)
790; RV32I-NEXT: addi a0, a0, 7
791; RV32I-NEXT: andi a0, a0, -4
792; RV32I-NEXT: addi a3, a0, 4
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]793; RV32I-NEXT: sw a3, 4(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]794; RV32I-NEXT: add a1, a1, s1
795; RV32I-NEXT: add a1, a1, a2
796; RV32I-NEXT: lw a0, 0(a0)
797; RV32I-NEXT: add a0, a1, a0
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]798; RV32I-NEXT: lw s1, 8(sp)
799; RV32I-NEXT: lw ra, 12(sp)
800; RV32I-NEXT: addi sp, sp, 48
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]801; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]802; RV32I-FPELIM-LABEL: va4_va_copy:
803; RV32I-FPELIM: # %bb.0:
804; RV32I-FPELIM-NEXT: addi sp, sp, -48
805; RV32I-FPELIM-NEXT: sw ra, 12(sp)
806; RV32I-FPELIM-NEXT: sw s1, 8(sp)
807; RV32I-FPELIM-NEXT: sw a1, 20(sp)
808; RV32I-FPELIM-NEXT: sw a7, 44(sp)
809; RV32I-FPELIM-NEXT: sw a6, 40(sp)
810; RV32I-FPELIM-NEXT: sw a5, 36(sp)
811; RV32I-FPELIM-NEXT: sw a4, 32(sp)
812; RV32I-FPELIM-NEXT: sw a3, 28(sp)
813; RV32I-FPELIM-NEXT: sw a2, 24(sp)
814; RV32I-FPELIM-NEXT: addi a0, sp, 24
815; RV32I-FPELIM-NEXT: sw a0, 4(sp)
816; RV32I-FPELIM-NEXT: sw a0, 0(sp)
817; RV32I-FPELIM-NEXT: lw s1, 20(sp)
818; RV32I-FPELIM-NEXT: lui a1, %hi(notdead)
819; RV32I-FPELIM-NEXT: addi a1, a1, %lo(notdead)
820; RV32I-FPELIM-NEXT: jalr a1
821; RV32I-FPELIM-NEXT: lw a0, 4(sp)
822; RV32I-FPELIM-NEXT: addi a0, a0, 3
823; RV32I-FPELIM-NEXT: andi a0, a0, -4
824; RV32I-FPELIM-NEXT: addi a1, a0, 4
825; RV32I-FPELIM-NEXT: sw a1, 4(sp)
826; RV32I-FPELIM-NEXT: lw a1, 0(a0)
827; RV32I-FPELIM-NEXT: addi a0, a0, 7
828; RV32I-FPELIM-NEXT: andi a0, a0, -4
829; RV32I-FPELIM-NEXT: addi a2, a0, 4
830; RV32I-FPELIM-NEXT: sw a2, 4(sp)
831; RV32I-FPELIM-NEXT: lw a2, 0(a0)
832; RV32I-FPELIM-NEXT: addi a0, a0, 7
833; RV32I-FPELIM-NEXT: andi a0, a0, -4
834; RV32I-FPELIM-NEXT: addi a3, a0, 4
835; RV32I-FPELIM-NEXT: sw a3, 4(sp)
836; RV32I-FPELIM-NEXT: add a1, a1, s1
837; RV32I-FPELIM-NEXT: add a1, a1, a2
838; RV32I-FPELIM-NEXT: lw a0, 0(a0)
839; RV32I-FPELIM-NEXT: add a0, a1, a0
840; RV32I-FPELIM-NEXT: lw s1, 8(sp)
841; RV32I-FPELIM-NEXT: lw ra, 12(sp)
842; RV32I-FPELIM-NEXT: addi sp, sp, 48
843; RV32I-FPELIM-NEXT: ret
844;
845; RV32I-WITHFP-LABEL: va4_va_copy:
846; RV32I-WITHFP: # %bb.0:
847; RV32I-WITHFP-NEXT: addi sp, sp, -64
848; RV32I-WITHFP-NEXT: sw ra, 28(sp)
849; RV32I-WITHFP-NEXT: sw s0, 24(sp)
850; RV32I-WITHFP-NEXT: sw s1, 20(sp)
851; RV32I-WITHFP-NEXT: addi s0, sp, 32
852; RV32I-WITHFP-NEXT: sw a1, 4(s0)
853; RV32I-WITHFP-NEXT: sw a7, 28(s0)
854; RV32I-WITHFP-NEXT: sw a6, 24(s0)
855; RV32I-WITHFP-NEXT: sw a5, 20(s0)
856; RV32I-WITHFP-NEXT: sw a4, 16(s0)
857; RV32I-WITHFP-NEXT: sw a3, 12(s0)
858; RV32I-WITHFP-NEXT: sw a2, 8(s0)
859; RV32I-WITHFP-NEXT: addi a0, s0, 8
860; RV32I-WITHFP-NEXT: sw a0, -16(s0)
861; RV32I-WITHFP-NEXT: sw a0, -20(s0)
862; RV32I-WITHFP-NEXT: lw s1, 4(s0)
863; RV32I-WITHFP-NEXT: lui a1, %hi(notdead)
864; RV32I-WITHFP-NEXT: addi a1, a1, %lo(notdead)
865; RV32I-WITHFP-NEXT: jalr a1
866; RV32I-WITHFP-NEXT: lw a0, -16(s0)
867; RV32I-WITHFP-NEXT: addi a0, a0, 3
868; RV32I-WITHFP-NEXT: andi a0, a0, -4
869; RV32I-WITHFP-NEXT: addi a1, a0, 4
870; RV32I-WITHFP-NEXT: sw a1, -16(s0)
871; RV32I-WITHFP-NEXT: lw a1, 0(a0)
872; RV32I-WITHFP-NEXT: addi a0, a0, 7
873; RV32I-WITHFP-NEXT: andi a0, a0, -4
874; RV32I-WITHFP-NEXT: addi a2, a0, 4
875; RV32I-WITHFP-NEXT: sw a2, -16(s0)
876; RV32I-WITHFP-NEXT: lw a2, 0(a0)
877; RV32I-WITHFP-NEXT: addi a0, a0, 7
878; RV32I-WITHFP-NEXT: andi a0, a0, -4
879; RV32I-WITHFP-NEXT: addi a3, a0, 4
880; RV32I-WITHFP-NEXT: sw a3, -16(s0)
881; RV32I-WITHFP-NEXT: add a1, a1, s1
882; RV32I-WITHFP-NEXT: add a1, a1, a2
883; RV32I-WITHFP-NEXT: lw a0, 0(a0)
884; RV32I-WITHFP-NEXT: add a0, a1, a0
885; RV32I-WITHFP-NEXT: lw s1, 20(sp)
886; RV32I-WITHFP-NEXT: lw s0, 24(sp)
887; RV32I-WITHFP-NEXT: lw ra, 28(sp)
888; RV32I-WITHFP-NEXT: addi sp, sp, 64
889; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]890 %vargs = alloca i8*, align 4
891 %wargs = alloca i8*, align 4
892 %1 = bitcast i8** %vargs to i8*
893 %2 = bitcast i8** %wargs to i8*
894 call void @llvm.va_start(i8* %1)
895 %3 = va_arg i8** %vargs, i32
896 call void @llvm.va_copy(i8* %2, i8* %1)
897 %4 = load i8*, i8** %wargs, align 4
898 call void @notdead(i8* %4)
899 %5 = va_arg i8** %vargs, i32
900 %6 = va_arg i8** %vargs, i32
901 %7 = va_arg i8** %vargs, i32
902 call void @llvm.va_end(i8* %1)
903 call void @llvm.va_end(i8* %2)
904 %add1 = add i32 %5, %3
905 %add2 = add i32 %add1, %6
906 %add3 = add i32 %add2, %7
907 ret i32 %add3
908}
909
910; Check 2x*xlen values are aligned appropriately when passed on the stack in a vararg call
911
912define i32 @va5_aligned_stack_callee(i32 %a, ...) nounwind {
913; RV32I-LABEL: va5_aligned_stack_callee:
914; RV32I: # %bb.0:
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]915; RV32I-NEXT: addi sp, sp, -32
916; RV32I-NEXT: sw a7, 28(sp)
917; RV32I-NEXT: sw a6, 24(sp)
918; RV32I-NEXT: sw a5, 20(sp)
919; RV32I-NEXT: sw a4, 16(sp)
920; RV32I-NEXT: sw a3, 12(sp)
921; RV32I-NEXT: sw a2, 8(sp)
922; RV32I-NEXT: sw a1, 4(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]923; RV32I-NEXT: addi a0, zero, 1
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]924; RV32I-NEXT: addi sp, sp, 32
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]925; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]926; RV32I-FPELIM-LABEL: va5_aligned_stack_callee:
927; RV32I-FPELIM: # %bb.0:
928; RV32I-FPELIM-NEXT: addi sp, sp, -32
929; RV32I-FPELIM-NEXT: sw a7, 28(sp)
930; RV32I-FPELIM-NEXT: sw a6, 24(sp)
931; RV32I-FPELIM-NEXT: sw a5, 20(sp)
932; RV32I-FPELIM-NEXT: sw a4, 16(sp)
933; RV32I-FPELIM-NEXT: sw a3, 12(sp)
934; RV32I-FPELIM-NEXT: sw a2, 8(sp)
935; RV32I-FPELIM-NEXT: sw a1, 4(sp)
936; RV32I-FPELIM-NEXT: addi a0, zero, 1
937; RV32I-FPELIM-NEXT: addi sp, sp, 32
938; RV32I-FPELIM-NEXT: ret
939;
940; RV32I-WITHFP-LABEL: va5_aligned_stack_callee:
941; RV32I-WITHFP: # %bb.0:
942; RV32I-WITHFP-NEXT: addi sp, sp, -48
943; RV32I-WITHFP-NEXT: sw ra, 12(sp)
944; RV32I-WITHFP-NEXT: sw s0, 8(sp)
945; RV32I-WITHFP-NEXT: addi s0, sp, 16
946; RV32I-WITHFP-NEXT: sw a7, 28(s0)
947; RV32I-WITHFP-NEXT: sw a6, 24(s0)
948; RV32I-WITHFP-NEXT: sw a5, 20(s0)
949; RV32I-WITHFP-NEXT: sw a4, 16(s0)
950; RV32I-WITHFP-NEXT: sw a3, 12(s0)
951; RV32I-WITHFP-NEXT: sw a2, 8(s0)
952; RV32I-WITHFP-NEXT: sw a1, 4(s0)
953; RV32I-WITHFP-NEXT: addi a0, zero, 1
954; RV32I-WITHFP-NEXT: lw s0, 8(sp)
955; RV32I-WITHFP-NEXT: lw ra, 12(sp)
956; RV32I-WITHFP-NEXT: addi sp, sp, 48
957; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]958 ret i32 1
959}
960
961define void @va5_aligned_stack_caller() nounwind {
962; The double should be 8-byte aligned on the stack, but the two-element array
963; should only be 4-byte aligned
964; RV32I-LABEL: va5_aligned_stack_caller:
965; RV32I: # %bb.0:
966; RV32I-NEXT: addi sp, sp, -64
967; RV32I-NEXT: sw ra, 60(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]968; RV32I-NEXT: addi a0, zero, 17
969; RV32I-NEXT: sw a0, 24(sp)
970; RV32I-NEXT: addi a0, zero, 16
971; RV32I-NEXT: sw a0, 20(sp)
972; RV32I-NEXT: addi a0, zero, 15
973; RV32I-NEXT: sw a0, 16(sp)
974; RV32I-NEXT: lui a0, 262236
975; RV32I-NEXT: addi a0, a0, 655
976; RV32I-NEXT: sw a0, 12(sp)
977; RV32I-NEXT: lui a0, 377487
978; RV32I-NEXT: addi a0, a0, 1475
979; RV32I-NEXT: sw a0, 8(sp)
980; RV32I-NEXT: addi a0, zero, 14
981; RV32I-NEXT: sw a0, 0(sp)
982; RV32I-NEXT: lui a0, 262153
983; RV32I-NEXT: addi a0, a0, 491
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]984; RV32I-NEXT: sw a0, 44(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]985; RV32I-NEXT: lui a0, 545260
986; RV32I-NEXT: addi a0, a0, -1967
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]987; RV32I-NEXT: sw a0, 40(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]988; RV32I-NEXT: lui a0, 964690
989; RV32I-NEXT: addi a0, a0, -328
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]990; RV32I-NEXT: sw a0, 36(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]991; RV32I-NEXT: lui a0, 335544
992; RV32I-NEXT: addi a0, a0, 1311
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]993; RV32I-NEXT: sw a0, 32(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]994; RV32I-NEXT: lui a0, 688509
995; RV32I-NEXT: addi a6, a0, -2048
996; RV32I-NEXT: lui a0, %hi(va5_aligned_stack_callee)
997; RV32I-NEXT: addi a5, a0, %lo(va5_aligned_stack_callee)
998; RV32I-NEXT: addi a0, zero, 1
999; RV32I-NEXT: addi a1, zero, 11
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]1000; RV32I-NEXT: addi a2, sp, 32
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]1001; RV32I-NEXT: addi a3, zero, 12
1002; RV32I-NEXT: addi a4, zero, 13
1003; RV32I-NEXT: addi a7, zero, 4
1004; RV32I-NEXT: jalr a5
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]1005; RV32I-NEXT: lw ra, 60(sp)
1006; RV32I-NEXT: addi sp, sp, 64
1007; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]1008; RV32I-FPELIM-LABEL: va5_aligned_stack_caller:
1009; RV32I-FPELIM: # %bb.0:
1010; RV32I-FPELIM-NEXT: addi sp, sp, -64
1011; RV32I-FPELIM-NEXT: sw ra, 60(sp)
1012; RV32I-FPELIM-NEXT: addi a0, zero, 17
1013; RV32I-FPELIM-NEXT: sw a0, 24(sp)
1014; RV32I-FPELIM-NEXT: addi a0, zero, 16
1015; RV32I-FPELIM-NEXT: sw a0, 20(sp)
1016; RV32I-FPELIM-NEXT: addi a0, zero, 15
1017; RV32I-FPELIM-NEXT: sw a0, 16(sp)
1018; RV32I-FPELIM-NEXT: lui a0, 262236
1019; RV32I-FPELIM-NEXT: addi a0, a0, 655
1020; RV32I-FPELIM-NEXT: sw a0, 12(sp)
1021; RV32I-FPELIM-NEXT: lui a0, 377487
1022; RV32I-FPELIM-NEXT: addi a0, a0, 1475
1023; RV32I-FPELIM-NEXT: sw a0, 8(sp)
1024; RV32I-FPELIM-NEXT: addi a0, zero, 14
1025; RV32I-FPELIM-NEXT: sw a0, 0(sp)
1026; RV32I-FPELIM-NEXT: lui a0, 262153
1027; RV32I-FPELIM-NEXT: addi a0, a0, 491
1028; RV32I-FPELIM-NEXT: sw a0, 44(sp)
1029; RV32I-FPELIM-NEXT: lui a0, 545260
1030; RV32I-FPELIM-NEXT: addi a0, a0, -1967
1031; RV32I-FPELIM-NEXT: sw a0, 40(sp)
1032; RV32I-FPELIM-NEXT: lui a0, 964690
1033; RV32I-FPELIM-NEXT: addi a0, a0, -328
1034; RV32I-FPELIM-NEXT: sw a0, 36(sp)
1035; RV32I-FPELIM-NEXT: lui a0, 335544
1036; RV32I-FPELIM-NEXT: addi a0, a0, 1311
1037; RV32I-FPELIM-NEXT: sw a0, 32(sp)
1038; RV32I-FPELIM-NEXT: lui a0, 688509
1039; RV32I-FPELIM-NEXT: addi a6, a0, -2048
1040; RV32I-FPELIM-NEXT: lui a0, %hi(va5_aligned_stack_callee)
1041; RV32I-FPELIM-NEXT: addi a5, a0, %lo(va5_aligned_stack_callee)
1042; RV32I-FPELIM-NEXT: addi a0, zero, 1
1043; RV32I-FPELIM-NEXT: addi a1, zero, 11
1044; RV32I-FPELIM-NEXT: addi a2, sp, 32
1045; RV32I-FPELIM-NEXT: addi a3, zero, 12
1046; RV32I-FPELIM-NEXT: addi a4, zero, 13
1047; RV32I-FPELIM-NEXT: addi a7, zero, 4
1048; RV32I-FPELIM-NEXT: jalr a5
1049; RV32I-FPELIM-NEXT: lw ra, 60(sp)
1050; RV32I-FPELIM-NEXT: addi sp, sp, 64
1051; RV32I-FPELIM-NEXT: ret
1052;
1053; RV32I-WITHFP-LABEL: va5_aligned_stack_caller:
1054; RV32I-WITHFP: # %bb.0:
1055; RV32I-WITHFP-NEXT: addi sp, sp, -64
1056; RV32I-WITHFP-NEXT: sw ra, 60(sp)
1057; RV32I-WITHFP-NEXT: sw s0, 56(sp)
1058; RV32I-WITHFP-NEXT: addi s0, sp, 64
1059; RV32I-WITHFP-NEXT: addi a0, zero, 17
1060; RV32I-WITHFP-NEXT: sw a0, 24(sp)
1061; RV32I-WITHFP-NEXT: addi a0, zero, 16
1062; RV32I-WITHFP-NEXT: sw a0, 20(sp)
1063; RV32I-WITHFP-NEXT: addi a0, zero, 15
1064; RV32I-WITHFP-NEXT: sw a0, 16(sp)
1065; RV32I-WITHFP-NEXT: lui a0, 262236
1066; RV32I-WITHFP-NEXT: addi a0, a0, 655
1067; RV32I-WITHFP-NEXT: sw a0, 12(sp)
1068; RV32I-WITHFP-NEXT: lui a0, 377487
1069; RV32I-WITHFP-NEXT: addi a0, a0, 1475
1070; RV32I-WITHFP-NEXT: sw a0, 8(sp)
1071; RV32I-WITHFP-NEXT: addi a0, zero, 14
1072; RV32I-WITHFP-NEXT: sw a0, 0(sp)
1073; RV32I-WITHFP-NEXT: lui a0, 262153
1074; RV32I-WITHFP-NEXT: addi a0, a0, 491
1075; RV32I-WITHFP-NEXT: sw a0, -20(s0)
1076; RV32I-WITHFP-NEXT: lui a0, 545260
1077; RV32I-WITHFP-NEXT: addi a0, a0, -1967
1078; RV32I-WITHFP-NEXT: sw a0, -24(s0)
1079; RV32I-WITHFP-NEXT: lui a0, 964690
1080; RV32I-WITHFP-NEXT: addi a0, a0, -328
1081; RV32I-WITHFP-NEXT: sw a0, -28(s0)
1082; RV32I-WITHFP-NEXT: lui a0, 335544
1083; RV32I-WITHFP-NEXT: addi a0, a0, 1311
1084; RV32I-WITHFP-NEXT: sw a0, -32(s0)
1085; RV32I-WITHFP-NEXT: lui a0, 688509
1086; RV32I-WITHFP-NEXT: addi a6, a0, -2048
1087; RV32I-WITHFP-NEXT: lui a0, %hi(va5_aligned_stack_callee)
1088; RV32I-WITHFP-NEXT: addi a5, a0, %lo(va5_aligned_stack_callee)
1089; RV32I-WITHFP-NEXT: addi a0, zero, 1
1090; RV32I-WITHFP-NEXT: addi a1, zero, 11
1091; RV32I-WITHFP-NEXT: addi a2, s0, -32
1092; RV32I-WITHFP-NEXT: addi a3, zero, 12
1093; RV32I-WITHFP-NEXT: addi a4, zero, 13
1094; RV32I-WITHFP-NEXT: addi a7, zero, 4
1095; RV32I-WITHFP-NEXT: jalr a5
1096; RV32I-WITHFP-NEXT: lw s0, 56(sp)
1097; RV32I-WITHFP-NEXT: lw ra, 60(sp)
1098; RV32I-WITHFP-NEXT: addi sp, sp, 64
1099; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]1100 %1 = call i32 (i32, ...) @va5_aligned_stack_callee(i32 1, i32 11,
1101 fp128 0xLEB851EB851EB851F400091EB851EB851, i32 12, i32 13, i64 20000000000,
1102 i32 14, double 2.720000e+00, i32 15, [2 x i32] [i32 16, i32 17])
1103 ret void
1104}
1105
1106; A function with no fixed arguments is not valid C, but can be
1107; specified in LLVM IR. We must ensure the vararg save area is
1108; still set up correctly.
1109
1110define i32 @va6_no_fixed_args(...) nounwind {
1111; RV32I-LABEL: va6_no_fixed_args:
1112; RV32I: # %bb.0:
1113; RV32I-NEXT: addi sp, sp, -48
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]1114; RV32I-NEXT: sw a0, 16(sp)
1115; RV32I-NEXT: sw a7, 44(sp)
1116; RV32I-NEXT: sw a6, 40(sp)
1117; RV32I-NEXT: sw a5, 36(sp)
1118; RV32I-NEXT: sw a4, 32(sp)
1119; RV32I-NEXT: sw a3, 28(sp)
1120; RV32I-NEXT: sw a2, 24(sp)
1121; RV32I-NEXT: sw a1, 20(sp)
1122; RV32I-NEXT: addi a0, sp, 20
1123; RV32I-NEXT: sw a0, 12(sp)
1124; RV32I-NEXT: lw a0, 16(sp)
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]1125; RV32I-NEXT: addi sp, sp, 48
1126; RV32I-NEXT: ret
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame^]1127; RV32I-FPELIM-LABEL: va6_no_fixed_args:
1128; RV32I-FPELIM: # %bb.0:
1129; RV32I-FPELIM-NEXT: addi sp, sp, -48
1130; RV32I-FPELIM-NEXT: sw a0, 16(sp)
1131; RV32I-FPELIM-NEXT: sw a7, 44(sp)
1132; RV32I-FPELIM-NEXT: sw a6, 40(sp)
1133; RV32I-FPELIM-NEXT: sw a5, 36(sp)
1134; RV32I-FPELIM-NEXT: sw a4, 32(sp)
1135; RV32I-FPELIM-NEXT: sw a3, 28(sp)
1136; RV32I-FPELIM-NEXT: sw a2, 24(sp)
1137; RV32I-FPELIM-NEXT: sw a1, 20(sp)
1138; RV32I-FPELIM-NEXT: addi a0, sp, 20
1139; RV32I-FPELIM-NEXT: sw a0, 12(sp)
1140; RV32I-FPELIM-NEXT: lw a0, 16(sp)
1141; RV32I-FPELIM-NEXT: addi sp, sp, 48
1142; RV32I-FPELIM-NEXT: ret
1143;
1144; RV32I-WITHFP-LABEL: va6_no_fixed_args:
1145; RV32I-WITHFP: # %bb.0:
1146; RV32I-WITHFP-NEXT: addi sp, sp, -48
1147; RV32I-WITHFP-NEXT: sw ra, 12(sp)
1148; RV32I-WITHFP-NEXT: sw s0, 8(sp)
1149; RV32I-WITHFP-NEXT: addi s0, sp, 16
1150; RV32I-WITHFP-NEXT: sw a0, 0(s0)
1151; RV32I-WITHFP-NEXT: sw a7, 28(s0)
1152; RV32I-WITHFP-NEXT: sw a6, 24(s0)
1153; RV32I-WITHFP-NEXT: sw a5, 20(s0)
1154; RV32I-WITHFP-NEXT: sw a4, 16(s0)
1155; RV32I-WITHFP-NEXT: sw a3, 12(s0)
1156; RV32I-WITHFP-NEXT: sw a2, 8(s0)
1157; RV32I-WITHFP-NEXT: sw a1, 4(s0)
1158; RV32I-WITHFP-NEXT: addi a0, s0, 4
1159; RV32I-WITHFP-NEXT: sw a0, -12(s0)
1160; RV32I-WITHFP-NEXT: lw a0, 0(s0)
1161; RV32I-WITHFP-NEXT: lw s0, 8(sp)
1162; RV32I-WITHFP-NEXT: lw ra, 12(sp)
1163; RV32I-WITHFP-NEXT: addi sp, sp, 48
1164; RV32I-WITHFP-NEXT: ret
Alex Bradburyc85be0d2018-01-10 19:41:03 +0000[diff] [blame]1165 %va = alloca i8*, align 4
1166 %1 = bitcast i8** %va to i8*
1167 call void @llvm.va_start(i8* %1)
1168 %2 = va_arg i8** %va, i32
1169 call void @llvm.va_end(i8* %1)
1170 ret i32 %2
1171}