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Duncan P. N. Exon Smithf862f872015-07-10 22:13:43 +00001//===- MCSchedule.cpp - Scheduling ------------------------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the default scheduling model.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/MC/MCSchedule.h"
Andrea Di Biagiob9acf132018-04-15 17:32:17 +000015#include "llvm/MC/MCInstrDesc.h"
16#include "llvm/MC/MCInstrInfo.h"
Andrea Di Biagio30c1ba42018-03-13 15:22:13 +000017#include "llvm/MC/MCSubtargetInfo.h"
Duncan P. N. Exon Smithf787ed02015-07-10 22:17:49 +000018#include <type_traits>
Duncan P. N. Exon Smithf862f872015-07-10 22:13:43 +000019
20using namespace llvm;
21
22static_assert(std::is_pod<MCSchedModel>::value,
23 "We shouldn't have a static constructor here");
24const MCSchedModel MCSchedModel::Default = {DefaultIssueWidth,
25 DefaultMicroOpBufferSize,
26 DefaultLoopMicroOpBufferSize,
27 DefaultLoadLatency,
28 DefaultHighLatency,
29 DefaultMispredictPenalty,
30 false,
31 true,
32 0,
33 nullptr,
34 nullptr,
35 0,
36 0,
Andrea Di Biagio823e5f92018-04-03 13:52:26 +000037 nullptr,
Duncan P. N. Exon Smithf862f872015-07-10 22:13:43 +000038 nullptr};
Andrea Di Biagio30c1ba42018-03-13 15:22:13 +000039
40int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI,
41 const MCSchedClassDesc &SCDesc) {
42 int Latency = 0;
43 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries;
44 DefIdx != DefEnd; ++DefIdx) {
45 // Lookup the definition's write latency in SubtargetInfo.
46 const MCWriteLatencyEntry *WLEntry =
47 STI.getWriteLatencyEntry(&SCDesc, DefIdx);
48 // Early exit if we found an invalid latency.
49 if (WLEntry->Cycles < 0)
50 return WLEntry->Cycles;
51 Latency = std::max(Latency, static_cast<int>(WLEntry->Cycles));
52 }
53 return Latency;
54}
Andrea Di Biagio7faea7c2018-03-13 16:28:55 +000055
Andrea Di Biagiob9acf132018-04-15 17:32:17 +000056int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI,
57 unsigned SchedClass) const {
58 const MCSchedClassDesc &SCDesc = *getSchedClassDesc(SchedClass);
59 if (!SCDesc.isValid())
60 return 0;
61 if (!SCDesc.isVariant())
62 return MCSchedModel::computeInstrLatency(STI, SCDesc);
63
64 llvm_unreachable("unsupported variant scheduling class");
65}
Andrea Di Biagio7faea7c2018-03-13 16:28:55 +000066
67Optional<double>
68MCSchedModel::getReciprocalThroughput(const MCSubtargetInfo &STI,
69 const MCSchedClassDesc &SCDesc) {
70 Optional<double> Throughput;
Andrea Di Biagiob9acf132018-04-15 17:32:17 +000071 const MCSchedModel &SM = STI.getSchedModel();
72 const MCWriteProcResEntry *I = STI.getWriteProcResBegin(&SCDesc);
73 const MCWriteProcResEntry *E = STI.getWriteProcResEnd(&SCDesc);
74 for (; I != E; ++I) {
75 if (!I->Cycles)
76 continue;
77 unsigned NumUnits = SM.getProcResource(I->ProcResourceIdx)->NumUnits;
78 double Temp = NumUnits * 1.0 / I->Cycles;
79 Throughput = Throughput ? std::min(Throughput.getValue(), Temp) : Temp;
Andrea Di Biagio7faea7c2018-03-13 16:28:55 +000080 }
Andrea Di Biagiob9acf132018-04-15 17:32:17 +000081 return Throughput ? 1 / Throughput.getValue() : Throughput;
82}
Andrea Di Biagio7faea7c2018-03-13 16:28:55 +000083
Andrea Di Biagiob9acf132018-04-15 17:32:17 +000084Optional<double>
85MCSchedModel::getReciprocalThroughput(unsigned SchedClass,
86 const InstrItineraryData &IID) {
87 Optional<double> Throughput;
88 const InstrStage *I = IID.beginStage(SchedClass);
89 const InstrStage *E = IID.endStage(SchedClass);
90 for (; I != E; ++I) {
91 if (!I->getCycles())
92 continue;
93 double Temp = countPopulation(I->getUnits()) * 1.0 / I->getCycles();
94 Throughput = Throughput ? std::min(Throughput.getValue(), Temp) : Temp;
95 }
96 return Throughput ? 1 / Throughput.getValue() : Throughput;
Andrea Di Biagio7faea7c2018-03-13 16:28:55 +000097}