llvm/test/CodeGen/X86/div-rem-simplify.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s

; Div/rem by zero is undef.

define i32 @srem0(i32 %x) {
; CHECK-LABEL: srem0:
; CHECK:       # BB#0:
; CHECK-NEXT:    retq
  %rem = srem i32 %x, 0
  ret i32 %rem
}

define i32 @urem0(i32 %x) {
; CHECK-LABEL: urem0:
; CHECK:       # BB#0:
; CHECK-NEXT:    retq
  %rem = urem i32 %x, 0
  ret i32 %rem
}

define i32 @sdiv0(i32 %x) {
; CHECK-LABEL: sdiv0:
; CHECK:       # BB#0:
; CHECK-NEXT:    retq
  %div = sdiv i32 %x, 0
  ret i32 %div
}

define i32 @udiv0(i32 %x) {
; CHECK-LABEL: udiv0:
; CHECK:       # BB#0:
; CHECK-NEXT:    retq
  %div = udiv i32 %x, 0
  ret i32 %div
}

; Div/rem by zero vectors is undef.

define <4 x i32> @srem_vec0(<4 x i32> %x) {
; CHECK-LABEL: srem_vec0:
; CHECK:       # BB#0:
; CHECK-NEXT:    retq
  %rem = srem <4 x i32> %x, zeroinitializer
  ret <4 x i32> %rem
}

define <4 x i32> @urem_vec0(<4 x i32> %x) {
; CHECK-LABEL: urem_vec0:
; CHECK:       # BB#0:
; CHECK-NEXT:    retq
  %rem = urem <4 x i32> %x, zeroinitializer
  ret <4 x i32> %rem
}

define <4 x i32> @sdiv_vec0(<4 x i32> %x) {
; CHECK-LABEL: sdiv_vec0:
; CHECK:       # BB#0:
; CHECK-NEXT:    retq
  %div = sdiv <4 x i32> %x, zeroinitializer
  ret <4 x i32> %div
}

define <4 x i32> @udiv_vec0(<4 x i32> %x) {
; CHECK-LABEL: udiv_vec0:
; CHECK:       # BB#0:
; CHECK-NEXT:    retq
  %div = udiv <4 x i32> %x, zeroinitializer
  ret <4 x i32> %div
}