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gerrit-public.fairphone.software / toolchain / llvm-project / 7fa23fc78fdb0e56b83eab2c0f780d2bbe443c1d / . / llvm / test / MC / ARM / eh-directive-section-multiple-func.s
blob: 425cbd7d0158ba4157362ce121ea36ff885abec0 [file] [log] [blame]
Logan Chien4ea23b52013-05-10 16:17:24 +0000[diff] [blame]1@ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -filetype=obj -o - \
2@ RUN: | llvm-readobj -s -sd -sr -t | FileCheck %s
3
4@ Check whether the section is switched back properly.
5
6@ The assembler should switch the section back to the corresponding section
7@ after it have emitted the exception handling indices and tables. In this
8@ test case, we are checking whether the section is correct when .section
9@ directives is used.
10
11@ In this example, func1 and func2 should be defined in .TEST1 section.
12@ It is incorrect if the func2 is in .text, .ARM.extab.TEST1, or
13@ .ARM.exidx.TEST1 sections.
14
15 .syntax unified
16
17 .section .TEST1
18
19 .globl func1
20 .align 2
21 .type func1,%function
22 .fnstart
23func1:
24 bx lr
25 .personality __gxx_personality_v0
26 .handlerdata
27 .fnend
28
29 .globl func2
30 .align 2
31 .type func2,%function
32 .fnstart
33func2:
34 bx lr
35 .personality __gxx_personality_v0
36 .handlerdata
37 .fnend
38
39
40@-------------------------------------------------------------------------------
41@ Check the .text section. This should be empty.
42@-------------------------------------------------------------------------------
43@ CHECK: Sections [
44@ CHECK: Section {
45@ CHECK: Name: .text
46@ CHECK: SectionData (
47@ CHECK: )
48@ CHECK: }
49
50
51@-------------------------------------------------------------------------------
52@ Check the .TEST1 section. There should be two "bx lr" instructions.
53@-------------------------------------------------------------------------------
54@ CHECK: Section {
55@ CHECK: Name: .TEST1
56@ CHECK: SectionData (
57@ CHECK: 0000: 1EFF2FE1 1EFF2FE1 |../.../.|
58@ CHECK: )
59@ CHECK: }
60
61
62
63@-------------------------------------------------------------------------------
64@ Check the .ARM.extab.TEST1 section.
65@-------------------------------------------------------------------------------
66@ CHECK: Section {
67@ CHECK: Name: .ARM.extab.TEST1
Logan Chien4ea23b52013-05-10 16:17:24 +0000[diff] [blame]68@ CHECK: SectionData (
69@ CHECK: 0000: 00000000 B0B0B000 00000000 B0B0B000 |................|
70@ CHECK: )
71@ CHECK: }
Rafael Espindola7fa23fc2015-04-15 17:24:06 +0000[diff] [blame^]72
73@ CHECK: Section {
74@ CHECK: Name: .rel.ARM.extab.TEST1
Rafael Espindola4f60a382013-05-30 03:05:14 +0000[diff] [blame]75@ CHECK: Relocations [
76@ CHECK: 0x0 R_ARM_PREL31 __gxx_personality_v0 0x0
77@ CHECK: 0x8 R_ARM_PREL31 __gxx_personality_v0 0x0
78@ CHECK: ]
Rafael Espindola7fa23fc2015-04-15 17:24:06 +0000[diff] [blame^]79@ CHECK: }
Logan Chien4ea23b52013-05-10 16:17:24 +0000[diff] [blame]80
81
82@-------------------------------------------------------------------------------
83@ Check the .ARM.exidx.TEST1 section.
84@-------------------------------------------------------------------------------
85@ CHECK: Section {
86@ CHECK: Name: .ARM.exidx.TEST1
87@ CHECK: Link: 4
88@-------------------------------------------------------------------------------
Rafael Espindola4f60a382013-05-30 03:05:14 +0000[diff] [blame]89@ The first word should be the offset to .TEST1.
90@ The second word should be the offset to .ARM.extab.TEST1
91@-------------------------------------------------------------------------------
92@ CHECK: SectionData (
93@ CHECK: 0000: 00000000 00000000 04000000 08000000 |................|
94@ CHECK: )
95@ CHECK: }
Rafael Espindola4f60a382013-05-30 03:05:14 +0000[diff] [blame]96@-------------------------------------------------------------------------------
Logan Chien4ea23b52013-05-10 16:17:24 +0000[diff] [blame]97@ The first word of each entry should be relocated to .TEST1 section.
98@ The second word of each entry should be relocated to
99@ .ARM.extab.TESET1 section.
100@-------------------------------------------------------------------------------
Rafael Espindola7fa23fc2015-04-15 17:24:06 +0000[diff] [blame^]101
102@ CHECK: Section {
103@ CHECK: Name: .rel.ARM.exidx.TEST1
Logan Chien4ea23b52013-05-10 16:17:24 +0000[diff] [blame]104@ CHECK: Relocations [
105@ CHECK: 0x0 R_ARM_PREL31 .TEST1 0x0
106@ CHECK: 0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0
107@ CHECK: 0x8 R_ARM_PREL31 .TEST1 0x0
108@ CHECK: 0xC R_ARM_PREL31 .ARM.extab.TEST1 0x0
109@ CHECK: ]
Rafael Espindola7fa23fc2015-04-15 17:24:06 +0000[diff] [blame^]110@ CHECK: }
Logan Chien4ea23b52013-05-10 16:17:24 +0000[diff] [blame]111
112
113@-------------------------------------------------------------------------------
114@ Check the symbols "func1" and "func2". They should belong to .TEST1 section.
115@-------------------------------------------------------------------------------
116@ CHECK: Symbols [
117@ CHECK: Symbol {
118@ CHECK: Name: func1
119@ CHECK: Value: 0x0
120@ CHECK: Size: 0
121@ CHECK: Binding: Global (0x1)
122@ CHECK: Type: Function (0x2)
123@ CHECK: Other: 0
124@ CHECK: Section: .TEST1 (0x4)
125@ CHECK: }
126@ CHECK: Symbol {
127@ CHECK: Name: func2
128@ CHECK: Value: 0x4
129@ CHECK: Size: 0
130@ CHECK: Binding: Global (0x1)
131@ CHECK: Type: Function (0x2)
132@ CHECK: Other: 0
133@ CHECK: Section: .TEST1 (0x4)
134@ CHECK: }
135@ CHECK: ]